Resource constrained design of artificial neural networks. - Benjamin W. Wah; Harish Kriplani (IJCNN, 1990)

Maximum Current Estimation in CMOS Circuits. - Harish Kriplani; Farid N. Najm; Ibrahim N. Hajj (DAC, 1992)

Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits. - Harish Kriplani; Farid N. Najm; Ping Yang 001; Ibrahim N. Hajj (DAC, 1993)

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits. - Harish Kriplani; Farid N. Najm; Ibrahim N. Hajj (ISCAS, 1994)

Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution. - Harish Kriplani; Farid N. Najm; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Timing model extraction of hierarchical blocks by graph reduction. - Cho W. Moon; Harish Kriplani; Krishna P. Belkhale (DAC, 2002)