Space Vector Based Hybrid PWM Techniques for Reduced Current Ripple. - G. Narayanan; V. T. Ranganathan; Di Zhao; Harish K. Krishnamurthy; Rajapandian Ayyanar 001 (IEEE Trans. Ind. Electron., 2008)

Reduction of Torque Ripple in Induction Motor Drives Using an Advanced Hybrid PWM Technique. - Kaushik Basu; J. S. Siva Prasad; G. Narayanan; Harish K. Krishnamurthy; Rajapandian Ayyanar 001 (IEEE Trans. Ind. Electron., 2010)

Synthesizable delay line architectures for digitally controlled voltage regulators. - Omar Haridy; Harish Krishnamurthy; Amr Helmy; Yehea Ismail (SoCC, 2012)

Impact of process variation in inductive integrated voltage regulator on delay and power of digital circuits. - Monodeep Kar; Sergio Carlo; Harish Kumar Krishnamurthy; Saibal Mukhopadhyay (ISLPED, 2014)

A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS. - Harish Krishnamurthy; Vaibhav A. Vaidya; Pavan Kumar 001; George E. Matthew; Sheldon Weng; Bharani Thiruvengadam; Wayne Proefrock; Krishnan Ravichandran; Vivek De (VLSIC, 2014)

A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS. - Pavan Kumar 001; Vaibhav A. Vaidya; Harish Krishnamurthy; Stephen T. Kim; George E. Matthew; Sheldon Weng; Bharani Thiruvengadam; Wayne Proefrock; Krishnan Ravichandran; Vivek De (CICC, 2015)

Digitally controlled voltage regulator using oscillator-based ADC with fast-transient-response and wide dropout range in 14nm CMOS. - Tarun Mahajan; Ramnarayanan Muthukaruppan; Dheeraj M. Shetty; Sumedha Mangal; Harish Kumar Krishnamurthy (CICC, 2017)

A digitally controlled linear regulator for per-core wide-range DVFS of atom™ cores in 14nm tri-gate CMOS featuring non-linear control, adaptive gain and code roaming. - Ramnarayanan Muthukaruppan; Tarun Mahajan; Harish Kumar Krishnamurthy; Sumedha Mangal; Am Dhanashekar; Rupak Ghayal; Vivek De (ESSCIRC, 2017)

20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS. - Harish Kumar Krishnamurthy; Vaibhav A. Vaidya; Sheldon Weng; Krishnan Ravichandran; Pavan Kumar 001; Stephen T. Kim; Rinkle Jain; George E. Matthew; Jim Tschanz; Vivek De (ISSCC, 2017)

A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes. - Suhwan Kim 002; Vaibhav A. Vaidya; Christopher Schaef; Andrew Lines; Harish Krishnamurthy; Sheldon Weng; Xiaosen Liu; Dileep Kurian; Tanay Karnik; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2018)

A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS. - Harish Kumar Krishnamurthy; Vaibhav A. Vaidya; Pavan Kumar 001; Rinkle Jain; Sheldon Weng; Stephen T. Kim; George E. Matthew; Nachiket V. Desai; Xiaosen Liu; Krishnan Ravichandran; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2018)

A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS. - Harish Kumar Krishnamurthy; Sheldon Weng; George E. Matthew; Nachiket V. Desai; Ruchir Saraswat; Krishnan Ravichandran; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2018)

A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation. - Xiaosen Liu; Harish K. Krishnamurthy; Taesik Na; Sheldon Weng; Khondker Zakir Ahmed 001; Krishnan Ravichandran; James W. Tschanz; Vivek De (ISSCC, 2019)

A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation. - Christopher Schaef; Nachiket V. Desai; Harish Krishnamurthy; Sheldon Weng; Huong T. Do; William J. Lambert; Kaladhar Radhakrishnan; Krishnan Ravichandran; James W. Tschanz; Vivek De (ISSCC, 2019)

A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response. - Zakir K. Ahmed 001; Harish K. Krishnamurthy; Charles Augustine; Xiaosen Liu; Sheldon Weng; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2019)

A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors. - Christopher Schaef; Kaladhar Radhakrishnan; Krishnan Ravichandran; James W. Tschanz; Vivek De; Nachiket V. Desai; Harish K. Krishnamurthy; Xiaosen Liu; Khondker Zakir Ahmed 001; Suhwan Kim 002; Sheldon Weng; Huong T. Do; et al. (IEEE J. Solid State Circuits, 2019)

Digital Control of Switching and Linear Integrated Voltage Regulators. - Harish K. Krishnamurthy; Zakir A. Khondker 001; Xiaosen Liu; Nachiket V. Desai; Suhwan Kim 002; Nicolas Butzen; Sally Amin; Sheldon Weng; Krishnan Ravichandran; James W. Tschanz; Vivek De (CICC, 2020)

27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation. - Debayan Das; Josef Danial; Anupam Golder; Nirmoy Modak; Shovan Maity; Baibhab Chatterjee; Dong-Hyun Seo; Muya Chang; Avinash Varna 001; Harish Krishnamurthy; Sanu Mathew; Santosh Ghosh; et al. (ISSCC, 2020)

An Autonomous Reconfigurable Power Delivery Network (RPDN) for Many-Core SoCs Featuring Dynamic Current Steering. - Zakir K. Ahmed 001; Harish K. Krishnamurthy; Sheldon Weng; Xiaosen Liu; Christopher Schaef; Nachiket V. Desai; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2020)

A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures. - Raghavan Kumar; Xiaosen Liu; Vikram B. Suresh; Harish Krishnamurthy; Mark A. Anders 001; Himanshu Kaul; Krishnan Ravichandran; Vivek De; Sanu Mathew (VLSI Circuits, 2020)

A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency. - Xiaosen Liu; Harish K. Krishnamurthy; Claudia P. Barrera; Jing Han; Rajasekhara M. Narayana Bhatla; Scott Chiu; Zakir K. Ahmed 001; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2020)

A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response. - Khondker Zakir Ahmed 001; Harish K. Krishnamurthy; Charles Augustine; Xiaosen Liu; Sheldon Weng; Krishnan Ravichandran; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2020)

17.4 Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing. - Nachiket V. Desai; Harish K. Krishnamurthy; Khondker Zakir Ahmed 001; Sheldon Weng; Suhwan Kim 002; Xiaosen Liu; Huong T. Do; Kaladhar Radhakrishnan; Krishnan Ravichandran; James W. Tschanz; Vivek De (ISSCC, 2021)

Session 17 Overview: DC-DC Converters Power Management Subcommittee. - Li Geng; Harish Krishnamurthy; Gaël Pillonnet (ISSCC, 2021)

A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction. - Khondker Zakir Ahmed 001; Nachiket V. Desai; Harish K. Krishnamurthy; Sheldon Weng; Xiaosen Liu; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2021)

A 32A 5V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN NMOS Power Transistors. - Nachiket V. Desai; Harish K. Krishnamurthy; William J. Lambert; Jingshu Yu; Han Wui Then; Nicolas Butzen; Sheldon Weng; Christopher Schaef; N. Nidhi; Marko Radosavljevic; Johann Rode; Justin Sandford; et al. (VLSI Circuits, 2021)

A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers. - Suhwan Kim 002; Harish Krishnamurthy; Sally Amin; Sheldon Weng; Jin Feng; Huong T. Do; Kaladhar Radhakrishnan; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2021)

EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing. - Debayan Das; Josef Danial; Anupam Golder; Nirmoy Modak; Shovan Maity; Baibhab Chatterjee; Dong-Hyun Seo; Muya Chang; Avinash Varna 001; Harish K. Krishnamurthy; Sanu Mathew; Santosh Ghosh; et al. (IEEE J. Solid State Circuits, 2021)

A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS. - Raghavan Kumar; Xiaosen Liu; Vikram B. Suresh; Harish K. Krishnamurthy; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Krishnan Ravichandran; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2021)

A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning. - Xiaosen Liu; Harish K. Krishnamurthy; Taesik Na; Sheldon Weng; Khondker Zakir Ahmed 001; Christopher Schaef; Krishnan Ravichandran; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2021)

Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. - Sriram R. Vangal; Somnath Paul; Steven Hsu; Amit Agarwal 001; Saurabh Kumar 003; Ram Krishnamurthy 001; Harish Krishnamurthy; James W. Tschanz; Vivek De; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer. - Xiaosen Liu; Harish Krishnamurthy; Renzhi Liu; Krishnan Ravichandran; Zakir K. Ahmed 001; Nachiket V. Desai; Nicolas Butzen; James W. Tschanz; Vivek De (ISSCC, 2022)

Fully Integrated Voltage Regulators with Package-Embedded Inductors for Heterogeneous 3D-TSV-Stacked System-in-Package with 22nm CMOS Active Silicon Interposer Featuring Self-Trimmed, Digitally Controlled ON-Time Discontinuous Conduction Mode (DCM) Operation. - Nachiket V. Desai; Harish K. Krishnamurthy; Suhwan Kim 002; Christopher Schaef; Sheldon Weng; Beomseok Choi; William J. Lambert; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Technology and Circuits, 2022)

A 32-A, 5-V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors. - Nachiket V. Desai; Han Wui Then; Jingshu Yu; Harish K. Krishnamurthy; William J. Lambert; Nicolas Butzen; Sheldon Weng; Christopher Schaef; Kaladhar Radhakrishnan; Krishnan Ravichandran; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2022)

EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation. - Debayan Das; Mayukh Nath; Baibhab Chatterjee; Raghavan Kumar; Xiaosen Liu; Harish Krishnamurthy; Manoj R. Sastry; Sanu Mathew; Santosh Ghosh; Shreyas Sen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Monolithic 26A/mm2Imax, 88.5% Peak-Efficiency Continuously Scalable Conversion-Ratio Switched-Capacitor DC-DC Converter. - Nicolas Butzen; Harish Krishnamurthy; Zakir K. Ahmed 001; Sheldon Weng; Krishnan Ravichandran; Michael Zelikson; James W. Tschanz; Jonathan Douglas (ISSCC, 2023)

A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational Zero-Current Operation and Non-Linear Duty-Boost. - Suhwan Kim 002; Harish K. Krishnamurthy; Sergey Sofer; Sheldon Weng; Shahar Wolf; Ashoke Ravi; Krishnan Ravichandran; Ofir Degani; James W. Tschanz; Vivek De (ISSCC, 2023)

28.4 A Monolithic 12.7W/mm2 Pmax, 92% Peak-Efficiency CSCR-First Switched-Capacitor DC-DC Converter. - Nicolas Butzen; Harish Krishnamurthy; Jingshu Yu; Zakir K. Ahmed 001; Sheldon Weng; Krishnan Ravichandran; Ramez Hosseinian Ahangharnejhad; James Waldemer; Chris Pelto; James W. Tschanz (ISSCC, 2024)

14.9 A Monolithic 10.5W/mm2600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS. - Suhwan Kim 002; Harish K. Krishnamurthy; Zakir K. Ahmed 001; Nachiket V. Desai; Sheldon Weng; Anne Augustine; Huong T. Do; Jingshu Yu; Phong D. Bach; Xiaosen Liu; Kaladhar Radhakrishnan; Krishnan Ravichandran; et al. (ISSCC, 2024)

A 5.4V-Vin, 9.3A/mm2 10MHz Buck IVR Chiplet in 55nm BCD Featuring Self-Timed Bootstrap and Same-Cycle ZVS Control. - Sally Amin; Harish Krishnamurthy; Huong T. Do; Claudio Alvarez; Mike Hill; Kaladhar Radhakrishnan; Vivek De; Sheldon Weng; Krishnan Ravichandran; Jim Tschanz; Wilfred Gomes; Jonathan Douglas (VLSI Technology and Circuits, 2024)

A Monolithic 5.7A/mm2 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs. - Jingshu Yu; Xiaosen Liu; Minxiang Gong; Nicolas Butzen; Sheldon Weng; Harish K. Krishnamurthy; Krishnan Ravichandran; Ramez Hosseinian Ahangharnejhad; Jim Waldemer; Christopher Pelto; James W. Tschanz; Vivek De (VLSI Technology and Circuits, 2024)

A Monolithic 12.7 W/mm2, 92% Peak-Efficiency Switched-Capacitor DC-DC Converter Using CSCR-First Topology. - Nicolas Butzen; Harish K. Krishnamurthy; Jingshu Yu; Zakir K. Ahmed 001; Sheldon Weng; Krishnan Ravichandran; Ramez Hosseinian Ahangharnejhad; James Waldemer; Christopher Pelto; James W. Tschanz (IEEE J. Solid State Circuits, 2024)

8.8 Fine-Grained Spatial and Temporal Thermal Profiling of a 16nm CMOS Buck Converter and SoC Load-Current Emulator Using Low-Voltage Micron-Scale Thermal Sensors. - Zakir K. Ahmed 001; Suhwan Kim 002; Charles Augustine; Harish K. Krishnamurthy; Krishnan Ravichandran; James W. Tschanz; Vivek De (ISSCC, 2025)

A Monolithic, 10.5 W/mm2, 600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16 nm Class. - Suhwan Kim 002; Harish K. Krishnamurthy; Zakir K. Ahmed 001; Nachiket V. Desai; Sheldon Weng; Anne Augustine; Huong T. Do; Jingshu Yu; Phong D. Bach; Xiaosen Liu; Kaladhar Radhakrishnan; Krishnan Ravichandran; et al. (IEEE J. Solid State Circuits, 2025)

A Monolithic 5.7 A/mm2 91% Peak Efficiency Scalable Multistage Modular Switched Capacitor Voltage Regulator for Base Die Vertical Power Delivery in 3D-ICs. - Xiaosen Liu; Jingshu Yu; Minxiang Gong; Nicolas Butzen; Sheldon Weng; Harish K. Krishnamurthy; Krishnan Ravichandran; Ramez Hosseinian Ahangharnejhad; James Waldemer; Christopher Pelto; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2025)