HW/SW Co-Design for SoC on Mobile Platforms, invited. - Johan van der Tang; Harm van Rumpt; Dieter Kasperkovitz (IWSOC, 2005)

A Dual-Alternating-Slope Digital-to-Time Converter Leveraging Mismatch to Improve Delay Step Size. - Nimit Jain; Eric A. M. Klumperink; Harm van Rumpt; Bram Nauta (IEEE J. Solid State Circuits, 2025)