Test Generation for MOS Circuits. - Harry H. Chen; Robert G. Mathews; John A. Newkirk (ITC, 1984)

An Algorithm to Generate Tests for MOS Circuits at the Switch Level. - Harry H. Chen; Robert G. Mathews; John A. Newkirk (ITC, 1985)

Worst-Case Critical-Path Delay Analysis Considering Power-Supply Noise. - Fang Bao; Mohammad Tehranipoor; Harry H. Chen (Asian Test Symposium, 2013)

Predicting system-level test and in-field customer failures using data mining. - Harry H. Chen; Roger Hsu; PaulYoung Yang; J. J. Shyr (ITC, 2013)

Perspectives on Test Data Mining from Industrial Experience. - Harry H. Chen (ATS, 2014)

The case for analyzing system level failures using structural patterns. - Harry H. Chen (ITC, 2014)

System-level test coverage prediction by structural stress test data mining. - Bing-Yang Lin; Cheng-Wen Wu; Harry H. Chen (VLSI-DAT, 2015)

Cost reduction of system-level tests with stressed structural tests and SVM. - Jing-Jia Liou; Meng-Ta Hsieh; Jun-Fei Cherng; Harry H. Chen (VLSI-SoC, 2015)

Statistical techniques for predicting system-level failure using stress-test data. - Harry H. Chen; Shih-Hua Kuo; Jonathan Tung; Mango Chia-Tso Chao (VTS, 2015)

Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation. - Harry H. Chen; Simon Y.-H. Chen; Po-Yao Chuang; Cheng-Wen Wu (ATS, 2016)

Cell-aware test generation time reduction by using switch-level ATPG. - Po-Yao Chuang; Cheng-Wen Wu; Harry H. Chen (ITC-Asia, 2017)

Enhancing the efficiency and accuracy of cell-aware testing to reach zero defects. - Harry H. Chen (VLSI-DAT, 2017)

Covering hard-to-detect defects by thermal quorum sensing. - Po-Yao Chuang; Cheng-Wen Wu; Harry H. Chen (ETS, 2018)

Beyond structural test, the rising need for system-level test. - Harry H. Chen (VLSI-DAT, 2018)

Hardware and firmware verification and validation: an algorithm-to-firmware development methodology. - Henry Cox; Harry H. Chen (DATE, 2019)

An ISA-level Accurate Fault Simulator for System-level Fault Analysis. - Jiang-Tang Xiao; Ting-Shuo Hsu; Christian M. Fuchs; Yu-Teng Chang; Jing-Jia Liou; Harry H. Chen (ATS, 2020)

Comprehensive Quality and Reliability Management for Automotive Product. - M. H. Hsieh; W. S. Chiang; Harry H. Chen; M. Z. Lin; M. J. Lin (IRPS, 2020)

Innovative Test Practices in Asia. - Takeshi Iwasaki; Masao Aso; Haruji Futami; Satoshi Matsunaga; Yousuke Miyake; Takaaki Kato; Seiji Kajihara; Yukiya Miura; Smith Lai; Gavin Hung; Harry H. Chen; Haruo Kobayashi 001; et al. (VTS, 2020)

Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case Study. - Dun-An Yang; Jing-Jia Liou; Harry H. Chen (ATS, 2021)

35.1 An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoC. - Bo-Jr Huang; Eric Jia-Wei Fang; Sung S.-Y. Hsueh; Rory Huang; Angus Lin; Chi-Hsun Chiang; Yi-Hsuan Lin; Wen-Wen Hsieh; Barry Chen; Yi-Chang Zhuang; Cheng-Yuh Wu; Jia-Ming Chen; et al. (ISSCC, 2021)

ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph. - Dun-An Yang; Yu-Teng Chang; Ting-Shuo Hsu; Jing-Jia Liou; Harry H. Chen (ITC, 2021)

FPGA-Based Emulation for Accelerating Transient Fault Reduction Analysis. - Zih-Ming Huang; Dun-An Yang; Jing-Jia Liou; Harry H. Chen (ATS, 2022)

Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging. - Dun-An Yang; Jing-Jia Liou; Harry H. Chen (ITC, 2022)

Signal Reduction of Signature Blocks for Transient Fault Debugging. - Chun-Yeh Wang; Chien-Hsing Liang; Jing-Jia Liou; Harry H. Chen (ATS, 2023)

A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET. - Bo-Jr Huang; Alfred Tsai; Lear Hsieh; Kathleen Chang; C.-J. Tsai; Jia-Ming Chen; Eric Jia-Wei Fang; Sung S.-Y. Hsueh; Jack Ciao; Barry Chen; Chuck Chang; Ping Kao; et al. (ISSCC, 2023)

Vmin Prediction Using Nondestructive Stress Test. - Chun Chen; Jeng-Yu Liao; James Chien-Mo Li; Harry H. Chen; Eric Jia-Wei Fang (VTS, 2023)

14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU. - Chien-Yu Lu; Bo-Jr Huang; Min-Chieh Chen; Ollie Tsai; Alfred Tsai; Eric Jia-Wei Fang; Yuju Cho; Harry H. Chen; Ping Kao; Ericbill Wang; Hugh Mair; Shih-Arn Hwang (ISSCC, 2024)

Multi-core Vmin and Worst-core Vmin Prediction using SOMAC. - Jeng-Yu Liao; Li-Yang Wang; James Chien-Mo Li; Harry H. Chen (VTS, 2025)