A case study in computer-aided codesign of embedded controllers. - Luciano Lavagno; Massimiliano Chiodo; Paolo Giusto; Attila Jurecska; Harry Hsieh; S. Yee; Alberto L. Sangiovanni-Vincentelli; Kei Suzuki (CODES, 1994)

Hardware-software codesign of embedded systems. - Massimiliano Chiodo; Paolo Giusto; Attila Jurecska; Harry Hsieh; Alberto L. Sangiovanni-Vincentelli; Luciano Lavagno (IEEE Micro, 1994)

Synthesis of Software Programs for Embedded Control Applications. - Massimiliano Chiodo; Paolo Giusto; Attila Jurecska; Luciano Lavagno; Harry Hsieh; Kei Suzuki; Alberto L. Sangiovanni-Vincentelli; Ellen Sentovich (DAC, 1995)

Formal Verification of Embedded Systems based on CFSM Networks. - Felice Balarin; Harry Hsieh; Attila Jurecska; Luciano Lavagno; Alberto L. Sangiovanni-Vincentelli (DAC, 1996)

A case study in computer-aided co-design of embedded controllers. - Massimiliano Chiodo; Daniel W. Engels; Paolo Giusto; Harry Hsieh; Attila Jurecska; Luciano Lavagno; Kei Suzuki; Alberto L. Sangiovanni-Vincentelli (Des. Autom. Embed. Syst., 1996)

Modeling micro-controller peripherals for high-level co-simulation and synthesis. - Harry Hsieh; Alberto L. Sangiovanni-Vincentelli (CODES, 1997)

Synchronous equivalence for embedded systems: a tool for design exploration. - Harry Hsieh; Felice Balarin (ICCAD, 1999)

Synthesis of software programs for embedded control applications. - Felice Balarin; Massimiliano Chiodo; Paolo Giusto; Harry Hsieh; Attila Jurecska; Luciano Lavagno; Alberto L. Sangiovanni-Vincentelli; Ellen Sentovich; Kei Suzuki (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Efficient methods for embedded system design space exploration. - Harry Hsieh; Felice Balarin; Luciano Lavagno; Alberto L. Sangiovanni-Vincentelli (DAC, 2000)

Refining abstract equivalence analysis for embedded system design. - Harry Hsieh; Felice Balarin (HLDVT, 2000)

Synchronous approach to the functional equivalence of embeddedsystem implementations. - Harry Hsieh; Felice Balarin; Luciano Lavagno; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Formal verification of embedded system designs at multiple levels of abstraction. - Xi Chen 024; Fang Chen; Harry Hsieh; Felice Balarin; Yosinori Watanabe (HLDVT, 2002)

Simulation Trace Verification for Quantitative Constraints. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (Embedded Software for SoC, 2003)

Case Studies of Model Checking for Embedded System Designs. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (ACSD, 2003)

First results with eBlocks: embedded systems building blocks. - Susan Cotterell; Frank Vahid; Walid A. Najjar; Harry Hsieh (CODES+ISSS, 2003)

Automatic trace analysis for logic of constraints. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (DAC, 2003)

Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (DATE, 2003)

Verifying LOC based functional and performance constraints. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (HLDVT, 2003)

Metropolis: An Integrated Electronic System Design Environment. - Felice Balarin; Yosinori Watanabe; Harry Hsieh; Luciano Lavagno; Claudio Passerone; Alberto L. Sangiovanni-Vincentelli (Computer, 2003)

Formal Verification for Embedded System Designs. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (Des. Autom. Embed. Syst., 2003)

Utilizing Formal Assertions for System Design of Network Processors. - Xi Chen 024; Yan Luo 001; Harry Hsieh; Laxmi N. Bhuyan; Felice Balarin (DATE, 2004)

Assertion-based power/performance analysis of network processor architectures. - Jia Yu 008; Wei Wu 024; Xi Chen 024; Harry Hsieh; Jun Yang 002; Felice Balarin (HLDVT, 2004)

Assertion Based Verification and Analysis of Network Processor Architectures. - Xi Chen 024; Yan Luo 001; Harry Hsieh; Laxmi N. Bhuyan; Felice Balarin (Des. Autom. Embed. Syst., 2004)

Logic of constraints: a quantitative performance and functional constraint formalism. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Simulation based deadlock analysis for system level designs. - Xi Chen 024; Abhijit Davare; Harry Hsieh; Alberto L. Sangiovanni-Vincentelli; Yosinori Watanabe (DAC, 2005)

System Synthesis for Networks of Programmable Blocks. - Ryan Mannion; Harry Hsieh; Susan Cotterell; Frank Vahid (DATE, 2005)

Assertion-Based Design Exploration of DVS in Network Processor Architectures. - Jia Yu 008; Wei Wu 024; Xi Chen 024; Harry Hsieh; Jun Yang 002; Felice Balarin (DATE, 2005)

eBlocks - an enabling technology for basic sensor based systems. - Susan Cotterell; Ryan Mannion; Frank Vahid; Harry Hsieh (IPSN, 2005)

Communication and co-simulation infrastructure for heterogeneous system integration. - Guang Yang 004; Xi Chen 024; Felice Balarin; Harry Hsieh; Alberto L. Sangiovanni-Vincentelli (DATE, 2006)

Runtime Deadlock Analysis of SystemC Designs. - Eric Cheung; Piyush Satapathy; Vi Pham; Harry Hsieh; Xi Chen 024 (HLDVT, 2006)

Verification Approach of Metropolis Design Framework for Embedded Systems. - Xi Chen 024; Harry Hsieh; Felice Balarin (Int. J. Parallel Program., 2006)

Bridging RTL and gate: correlating different levels of abstraction for design debugging. - Eric Cheung; Xi Chen 024; Fur-Shing Tsai; Yu-Chin Hsu; Harry Hsieh (HLDVT, 2007)

Framework for fast and accurate performance simulation of multiprocessor systems. - Eric Cheung; Harry Hsieh; Felice Balarin (HLDVT, 2007)

Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip. - Eric Cheung; Harry Hsieh; Felice Balarin (HLDVT, 2007)

Software optimization for MPSoC: a mpeg-2 decoder case study. - Eric Cheung; Harry Hsieh; Felice Balarin (CODES+ISSS, 2008)

Partial order method for timed simulation of system-level MPSoC designs. - Eric Cheung; Harry Hsieh; Felice Balarin (ASP-DAC, 2009)

Fast and accurate performance simulation of embedded software for MPSoC. - Eric Cheung; Harry Hsieh; Felice Balarin (ASP-DAC, 2009)

Memory subsystem simulation in software TLM/T models. - Eric Cheung; Harry Hsieh; Felice Balarin (ASP-DAC, 2009)

Runtime deadlock analysis for system level design. - Eric Cheung; Xi Chen 024; Harry Hsieh; Abhijit Davare; Alberto L. Sangiovanni-Vincentelli; Yosinori Watanabe (Des. Autom. Embed. Syst., 2009)