Design for routability of a high-density gate array. - Dick W. Harberts; Dré A. J. M. van den Elshout; Harry J. M. Veendrick (ICCD, 1990)

An efficient and flexible architecture for high-density gate arrays. - Harry J. M. Veendrick; Dré A. J. M. van den Elshout; Dick W. Harberts; Teus Brand (IEEE J. Solid State Circuits, 1990)

Architecture and programming of two generations video signal processors. - Kees A. Vissers; Gerben Essink; Piet J. van Gerwen; P. J. M. Janssen; O. Popp; E. Riddersma; W. J. M. Smits; Harry J. M. Veendrick (Microprocess. Microprogramming, 1995)

Single Chip or Hybrid System Integration. - Ivo Bolsens; Wojtek Maly; Ludo Deferm; Jo Borel; Harry J. M. Veendrick (DATE, 1999)

Encoded-Low Swing Technique for Ultra Low Power Interconnect. - Rohini Krishnan; José Pineda de Gyvez; Harry J. M. Veendrick (FPL, 2003)

Adaptive threshold scheme to operate long on-chip buses at the limit of signal integrity. - Atul Katoch; Manish Garg; Evert Seevinck; Harry J. M. Veendrick (ESSCIRC, 2004)

Isodelay output driver design using step-wise charging for low power. - Atul Katoch; Harry J. M. Veendrick (ESSCIRC, 2005)

High speed current-mode signaling circuits for on-chip interconnects. - Atul Katoch; Harry J. M. Veendrick; Evert Seevinck (ISCAS (4), 2005)

A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs. - Violeta Petrescu; Marcel J. M. Pelgrom; Harry J. M. Veendrick; Praveen Pavithran; Jean Wieling (ISSCC, 2006)