A fine-line NMOS 3-Gbit/s 12 channel time-division multiplexer-demultiplexer chip set. - Robert Bayruns; Elizabeth A. Hofstatter; Harry T. Weston (IEEE J. Solid State Circuits, 1989)

A submicrometer NMOS multiplexer-demultiplexer chip set for 622.08-Mb/s SONET applications. - Harry T. Weston; Mihai Banu; San-Chin Fang; Philip W. Diodato; Thomas D. Stanik; Paul A. Wilford; Frank M. Hsu (IEEE J. Solid State Circuits, 1992)