Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory. - Kedar Janardan Dhori; Vinay Kumar; Harsh Rawat (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI. - Ramandeep Kaur; Alexander Fell; Harsh Rawat (SoCC, 2015)

FALPEM: Framework for Architectural-Level Power Estimation and Optimization for Large Memory Sub-Systems. - Amit Chhabra; Harsh Rawat; Mohit Jain; Pascal Tessier; Daniel Pierredon; Laurent Bergher; Promod Kumar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology. - Harsh Rawat; K. Bharath; Alexander Fell (SoCC, 2017)

Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS. - Mukesh Kumar Srivastav; Rimjhim; Govind Soni; Umang Mittal; Rupali Tewari; Riya Yadav; Anuj Grover; Kedar Janardan Dhori; Harsh Rawat (ICECS, 2021)

A Process and Data Variations Tolerant Capacitive Coupled 10T1C SRAM for In-Memory Compute (IMC) in Deep Neural Network Accelerators. - Belal Iqbal; Anuj Grover; Harsh Rawat (AICAS, 2022)

3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS. - Mukesh Kumar Srivastav; Rimjhim; Roshan Mishra; Anuj Grover; Kedar Janardan Dhori; Harsh Rawat (ISCAS, 2022)

Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI. - Chandan Kumar; Rahul Kumar; Anuj Grover; Shouri Chatterjee; Kedar Janardan Dhori; Harsh Rawat (VLSID, 2022)

A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications. - Giuseppe Desoli; Nitin Chawla; Thomas Boesch; Manui Avodhyawasi; Harsh Rawat; Hitesh Chawla; VS Abhijith; Paolo Zambotti; Akhilesh Sharma; Carmine Cappetta; Michele Rossi; Antonio De Vita; et al. (ISSCC, 2023)

A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute Applications in 65nm LSTP Technology. - Belal Iqbal; Anuj Grover; Harsh Rawat (VLSID, 2023)

AnalogSim: a Modeling Framework for SRAM-based Analog In-Memory Computing. - Talha Bin Aslam; Anuj Grover; Harsh Rawat (ISCAS, 2025)