A Highly Accurate Machine Learning Approach to Modelling PVT Variation Aware Leakage Power in FinFET Digital Circuits. - Shirisha Gourishetty; Harshini Mandadapu; Andleeb Zahra; Zia Abbas (APCCAS, 2019)

PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit Design. - Prateek Gupta; Shirisha Gourishetty; Harshini Mandadapu; Zia Abbas (ISCAS, 2019)

Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms. - Prateek Gupta; Harshini Mandadapu; Shirisha Gourishetty; Zia Abbas (ISQED, 2019)