A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture. - Toshiaki Kirihata; Martin Gall; Kohji Hosokawa; Jean-Marc Dortu; Hing Wong; Peter Pfefferl; Brian L. Ji; Oliver Weinfurtner; John K. DeBrosse; Hartmud Terletzki; Manfred Selz; Wayne Ellis; et al. (IEEE J. Solid State Circuits, 1998)

A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. - Toshiaki Kirihata; Gerhard Mueller; Brian Ji; Gerd Frankowsky; Joseph M. Ross; Hartmud Terletzki; Dmitry G. Netis; Oliver Weinfurtner; David R. Hanson; Gabriel Daniel; Louis Lu-Chen Hsu; Daniel W. Storaska; et al. (IEEE J. Solid State Circuits, 1999)

A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. - Heinz Hoenigschmid; Alexander Frey; John K. DeBrosse; Toshiaki Kirihata; Gerhard Mueller; Daniel W. Storaska; Gabriel Daniel; Gerd Frankowsky; Kevin P. Guay; David R. Hanson; Louis Lu-Chen Hsu; Brian Ji; et al. (IEEE J. Solid State Circuits, 2000)