18-GHz 1/8 dynamic frequency divider using Si bipolar technologies. - Haruhiko Ichino; Noboru Ishihara; Masao Suzuki; Shinsuke Konaka (IEEE J. Solid State Circuits, 1989)

12-Gb/s decision circuit IC using AlGaAs/GaAS HBT technology. - Haruhiko Ichino; Noboru Ishihara; Yoshiki Yamauchi; Osaake Nakajima; Koichi Nagata; Takumi Nittono (IEEE J. Solid State Circuits, 1990)

Comments on '18-GHz 1/8 dynamic frequency divider using Si bipolar technologies (and reply). - Rainer H. Derksen; Haruhiko Ichino (IEEE J. Solid State Circuits, 1991)

20 Gb/s digital SSIs using AlGaAs/GaAs heterojunction bipolar transistors for future optical transmission systems. - Haruhiko Ichino (IEEE J. Solid State Circuits, 1993)

High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology. - Kiyoshi Ishii; Haruhiko Ichino; Yoshiji Kobayashi; Chikara Yamaguchi (IEEE J. Solid State Circuits, 1994)

Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit. - Kiyoshi Ishii; Haruhiko Ichino; Chikara Yamaguchi (IEEE J. Solid State Circuits, 1994)

Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops. - Kiyoshi Ishii; Haruhiko Ichino; Minoru Togashi; Yoshiji Kobayashi; Chikara Yamaguchi (IEEE J. Solid State Circuits, 1995)

A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic. - Keiji Kishine; Yoshiji Kobayashi; Haruhiko Ichino (IEEE J. Solid State Circuits, 1997)

High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing. - Keiichi Koike; Kenji Kawai; Akira Onozawa; Yuichiro Takei; Yoshiji Kobayashi; Haruhiko Ichino (IEEE J. Solid State Circuits, 1998)

A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design. - Kenji Kawai; Keiichi Koike; Yuichiro Takei; Akira Onozawa; Hitoshi Obara; Haruhiko Ichino (IEEE J. Solid State Circuits, 1999)

A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs. - Keiji Kishine; Noboru Ishihara; Ken-ichi Takiguchi; Haruhiko Ichino (IEEE J. Solid State Circuits, 1999)

A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit. - Kiyoshi Ishii; Keiji Kishine; Haruhiko Ichino (ISCAS, 2000)

A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI. - Kenji Kawai; Haruhiko Ichino (IEEE J. Solid State Circuits, 2000)

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX. - Keiji Kishine; Kiyoshi Ishii; Haruhiko Ichino (IEEE J. Solid State Circuits, 2002)

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits. - Keiji Kishine; Kyoko Fujimoto; Satomi Kusanagi; Haruhiko Ichino (IEEE J. Solid State Circuits, 2004)

Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks. - Kazuhiko Terada; Kenji Kawai; Osamu Ishida; Keiji Kishine; Noboru Iwasaki; Haruhiko Ichino (IEICE Trans. Commun., 2005)

MAC protocol based on cross-layer design methodology for fast link in wireless communication systems. - Shoko Ohteru; Keiji Kishine; Haruhiko Ichino (IEICE Electron. Express, 2007)