Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis. - Haruhiko Terada; Takayuki Fukuoka; Akira Tsuchiya; Hidetoshi Onodera (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Erect of regularity-enhanced layout on printability and circuit performance of standard cells. - Hiroki Sunagawa; Haruhiko Terada; Akira Tsuchiya; Kazutoshi Kobayashi; Hidetoshi Onodera (ISQED, 2009)

Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. - Hiroki Sunagawa; Haruhiko Terada; Akira Tsuchiya; Kazutoshi Kobayashi; Hidetoshi Onodera (IPSJ Trans. Syst. LSI Des. Methodol., 2010)