FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. - Masanori Hariyama; Yasuhiro Kobayashi; Haruka Sasaki; Michitaka Kameyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. - Masanori Hariyama; Haruka Sasaki; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2005)