Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process. - Kodai Yamada; Haruki Maruoka; Jun Furuta; Kazutoshi Kobayashi (IRPS, 2018)

A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process. - Haruki Maruoka; Masashi Hifumi; Jun Furuta; Kazutoshi Kobayashi (IEICE Trans. Electron., 2018)