Development of wafer thinning and dicing technology for thin wafer. - Chuichi Miyazaki; Haruo Shimamoto; Toshihide Uematsu; Yoshiyuki Abe (3DIC, 2009)

Development of high accuracy wafer thinning and pickup technology for thin wafer. - Chuichi Miyazaki; Haruo Shimamoto; Toshihide Uematsu; Yoshiyuki Abe; Kosuke Kitaichi; Tadahiro Morifuji; Shoji Yasunaga (3DIC, 2010)

Development of high accuracy wafer thinning and pickup technology for thin wafer. - Kosuke Kitaichi; Haruo Shimamoto; Chuichi Miyazaki; Yoshiyuki Abe; Sigeaki Saito; Shoji Yasunaga (3DIC, 2011)

Analysis of thermal stress distribution for TSV with novel structure. - Wei Feng; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi (3DIC, 2014)

Wet cleaning process for high-yield via-last TSV formation. - Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi; Hidekazu Kikuchi; Azusa Yanagisawa; Akio Nakamura (3DIC, 2016)

Fabrication and stress analysis of annular-trench-isolated TSV. - Wei Feng; Tung Thanh Bui 001; Naoya Watanabe; Haruo Shimamoto; Masahiro Aoyagi; Katsuya Kikuchi (Microelectron. Reliab., 2016)

Validation of TSV thermo-mechanical simulation by stress measurement. - Wei Feng; Naoya Watanabe; Haruo Shimamoto; Masahiro Aoyagi; Katsuya Kikuchi (Microelectron. Reliab., 2016)

Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. - Samson Melamed; Naoya Watanabe; Shunsuke Nemoto; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi (Microelectron. Reliab., 2016)

Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits. - Samson Melamed; Naoya Watanabe; Shunsuke Nemoto; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi (Microelectron. Reliab., 2017)

Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core. - Wei Feng; Naoya Watanabe; Haruo Shimamoto; Masahiro Aoyagi; Katsuya Kikuchi (3DIC, 2019)

Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. - Takuji Miki; Makoto Nagata; Akihiro Tsukioka; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (3DIC, 2019)

Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. - Takuji Miki; Makoto Nagata; Hiroki Sonoda; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEEE J. Solid State Circuits, 2020)

Landside capacitor efficacy among multi-chip-module using Si-interposer. - Yuuki Araga; Ryo Kasai; Daisuke Tanaka; Yoshihide Murakami; Kyoshi Mihara; Kazuo Makida; Hiroki Sonoda; Makoto Nagata; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEICE Electron. Express, 2021)

Analysis and evaluation of noise coupling between through-silicon-vias. - Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEICE Electron. Express, 2021)