GPU based Parallel Image Processing Library for Embedded Systems. - Mustafa Cavus; Hakki Doganer Sumerkan; Osman Seckin Simsek; Hasan Hassan; Abdullah Giray Yaglikçi; Oguz Ergin (VISAPP (1), 2014)

ChargeCache: Reducing DRAM latency by exploiting row access locality. - Hasan Hassan; Gennady Pekhimenko; Nandita Vijaykumar; Vivek Seshadri; Donghyuk Lee; Oguz Ergin; Onur Mutlu (HPCA, 2016)

Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization. - Kevin K. Chang; Abhijith Kashyap; Hasan Hassan; Saugata Ghose; Kevin Hsieh; Donghyuk Lee; Tianshi Li 001; Gennady Pekhimenko; Samira Manabi Khan; Onur Mutlu (SIGMETRICS, 2016)

GateKeeper: Enabling Fast Pre-Alignment in DNA Short Read Mapping with a New Streaming Accelerator Architecture. - Mohammed Alser; Hasan Hassan; Hongyi Xin; Oguz Ergin; Onur Mutlu; Can Alkan (CoRR, 2016)

Reducing DRAM Access Latency by Exploiting DRAM Leakage Characteristics and Common Access Patterns. - Hasan Hassan (CoRR, 2016)

Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM. - Vivek Seshadri; Donghyuk Lee; Thomas Mullins; Hasan Hassan; Amirali Boroumand; Jeremie S. Kim; Michael A. Kozuch; Onur Mutlu; Phillip B. Gibbons; Todd C. Mowry (CoRR, 2016)

SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies. - Hasan Hassan; Nandita Vijaykumar; Samira Manabi Khan; Saugata Ghose; Kevin K. Chang; Gennady Pekhimenko; Donghyuk Lee; Oguz Ergin; Onur Mutlu (HPCA, 2017)

Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology. - Vivek Seshadri; Donghyuk Lee; Thomas Mullins; Hasan Hassan; Amirali Boroumand; Jeremie S. Kim; Michael A. Kozuch; Onur Mutlu; Phillip B. Gibbons; Todd C. Mowry (MICRO, 2017)

GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping. - Mohammed Alser; Hasan Hassan; Hongyi Xin; Oguz Ergin; Onur Mutlu; Can Alkan (Bioinform., 2017)

LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory. - Amirali Boroumand; Saugata Ghose; Minesh Patel; Hasan Hassan; Brandon Lucia; Kevin Hsieh; Krishna T. Malladi; Hongzhong Zheng; Onur Mutlu (IEEE Comput. Archit. Lett., 2017)

LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures. - Amirali Boroumand; Saugata Ghose; Minesh Patel; Hasan Hassan; Brandon Lucia; Nastaran Hajinazar; Kevin Hsieh; Krishna T. Malladi; Hongzhong Zheng; Onur Mutlu (CoRR, 2017)

Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms. - Kevin K. Chang; Abdullah Giray Yaglikçi; Saugata Ghose; Aditya Agrawal; Niladrish Chatterjee; Abhijith Kashyap; Donghyuk Lee; Mike O'Connor; Hasan Hassan; Onur Mutlu (CoRR, 2017)

Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms. - Kevin K. Chang; Abdullah Giray Yaglikçi; Saugata Ghose; Aditya Agrawal; Niladrish Chatterjee; Abhijith Kashyap; Donghyuk Lee; Mike O'Connor; Hasan Hassan; Onur Mutlu (Proc. ACM Meas. Anal. Comput. Syst., 2017)

VRL-DRAM: improving DRAM performance via variable refresh latency. - Anup Das 001; Hasan Hassan; Onur Mutlu (DAC, 2018)

The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices. - Jeremie S. Kim; Minesh Patel; Hasan Hassan; Onur Mutlu (HPCA, 2018)

Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines. - Jeremie S. Kim; Minesh Patel; Hasan Hassan; Onur Mutlu (ICCD, 2018)

Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration. - Yaohua Wang; Arash Tavakkol; Lois Orosa 001; Saugata Ghose; Nika Mansouri-Ghiasi; Minesh Patel; Jeremie S. Kim; Hasan Hassan; Mohammad Sadrosadati; Onur Mutlu (MICRO, 2018)

GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies. - Jeremie S. Kim; Damla Senol Cali; Hongyi Xin; Donghyuk Lee; Saugata Ghose; Mohammed Alser; Hasan Hassan; Oguz Ergin; Can Alkan; Onur Mutlu (BMC Genom., 2018)

Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips. - Kevin K. Chang; Abhijith Kashyap; Hasan Hassan; Saugata Ghose; Kevin Hsieh; Donghyuk Lee; Tianshi Li 001; Gennady Pekhimenko; Samira Manabi Khan; Onur Mutlu (CoRR, 2018)

Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency. - Kevin K. Chang; Abdullah Giray Yaglikçi; Saugata Ghose; Aditya Agrawal; Niladrish Chatterjee; Abhijith Kashyap; Donghyuk Lee; Mike O'Connor; Hasan Hassan; Onur Mutlu (CoRR, 2018)

SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure. - Hasan Hassan; Nandita Vijaykumar; Samira Manabi Khan; Saugata Ghose; Kevin K. Chang; Gennady Pekhimenko; Donghyuk Lee; Oguz Ergin; Onur Mutlu (CoRR, 2018)

Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency. - Hasan Hassan; Gennady Pekhimenko; Nandita Vijaykumar; Vivek Seshadri; Donghyuk Lee; Oguz Ergin; Onur Mutlu (CoRR, 2018)

D-RaNGe: Violating DRAM Timing Constraints for High-Throughput True Random Number Generation using Commodity DRAM Devices. - Jeremie S. Kim; Minesh Patel; Hasan Hassan; Lois Orosa 001; Onur Mutlu (CoRR, 2018)

SLIDER: Fast and Efficient Computation of Banded Sequence Alignment. - Mohammed Alser; Hasan Hassan; Akash Kumar 001; Onur Mutlu; Can Alkan (CoRR, 2018)

Enabling Efficient RDMA-based Synchronous Mirroring of Persistent Memory Transactions. - Arash Tavakkol; Aasheesh Kolli; Stanko Novakovic; Kaveh Razavi; Juan Gómez-Luna; Hasan Hassan; Claude Barthels; Yaohua Wang; Mohammad Sadrosadati; Saugata Ghose; Ankit Singla; Pratap Subrahmanyam; et al. (CoRR, 2018)

What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study. - Saugata Ghose; Abdullah Giray Yaglikçi; Raghav Gupta; Donghyuk Lee; Kais Kudrolli; William X. Liu; Hasan Hassan; Kevin K. Chang; Niladrish Chatterjee; Aditya Agrawal; Mike O'Connor; Onur Mutlu (Proc. ACM Meas. Anal. Comput. Syst., 2018)

Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices. - Minesh Patel; Jeremie S. Kim; Hasan Hassan; Onur Mutlu (DSN, 2019)

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput. - Jeremie S. Kim; Minesh Patel; Hasan Hassan; Lois Orosa 001; Onur Mutlu (HPCA, 2019)

CoNDA: efficient cache coherence support for near-data accelerators. - Amirali Boroumand; Saugata Ghose; Minesh Patel; Hasan Hassan; Brandon Lucia; Rachata Ausavarungnirun; Kevin Hsieh; Nastaran Hajinazar; Krishna T. Malladi; Hongzhong Zheng; Onur Mutlu (ISCA, 2019)

CROW: a low-cost substrate for improving DRAM performance, energy efficiency, and reliability. - Hasan Hassan; Minesh Patel; Jeremie S. Kim; Abdullah Giray Yaglikçi; Nandita Vijaykumar; Nika Mansouri-Ghiasi; Saugata Ghose; Onur Mutlu (ISCA, 2019)

Shouji: a fast and efficient pre-alignment filter for sequence alignment. - Mohammed Alser; Hasan Hassan; Akash Kumar 001; Onur Mutlu; Can Alkan (Bioinform., 2019)

Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices. - Lois Orosa 001; Yaohua Wang; Ivan Puddu; Mohammad Sadrosadati; Kaveh Razavi; Juan Gómez-Luna; Hasan Hassan; Nika Mansouri-Ghiasi; Arash Tavakkol; Minesh Patel; Jeremie S. Kim; Vivek Seshadri; et al. (CoRR, 2019)

Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques. - Jeremie S. Kim; Minesh Patel; Abdullah Giray Yaglikçi; Hasan Hassan; Roknoddin Azizi; Lois Orosa 001; Onur Mutlu (ISCA, 2020)

CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off. - Haocong Luo; Taha Shahroodi; Hasan Hassan; Minesh Patel; Abdullah Giray Yaglikçi; Lois Orosa 001; Jisung Park 001; Onur Mutlu (ISCA, 2020)

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics. - Minesh Patel; Jeremie S. Kim; Taha Shahroodi; Hasan Hassan; Onur Mutlu (MICRO, 2020)

TRRespass: Exploiting the Many Sides of Target Row Refresh. - Pietro Frigo; Emanuele Vannacci; Hasan Hassan; Victor van der Veen; Onur Mutlu; Cristiano Giuffrida; Herbert Bos; Kaveh Razavi (SP, 2020)

BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows. - Abdullah Giray Yaglikçi; Minesh Patel; Jeremie S. Kim; Roknoddin Azizi; Ataberk Olgun; Lois Orosa 001; Hasan Hassan; Jisung Park 001; Konstantinos Kanellopoulos; Taha Shahroodi; Saugata Ghose; Onur Mutlu (HPCA, 2021)

CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations. - Lois Orosa 001; Yaohua Wang; Mohammad Sadrosadati; Jeremie S. Kim; Minesh Patel; Ivan Puddu; Haocong Luo; Kaveh Razavi; Juan Gómez-Luna; Hasan Hassan; Nika Mansouri-Ghiasi; Saugata Ghose; et al. (ISCA, 2021)

A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chipsand Implications on Future Attacks and Defenses. - Lois Orosa 001; Abdullah Giray Yaglikçi; Haocong Luo; Ataberk Olgun; Jisung Park 001; Hasan Hassan; Minesh Patel; Jeremie S. Kim; Onur Mutlu (MICRO, 2021)

Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications. - Hasan Hassan; Yahya Can Tugrul; Jeremie S. Kim; Victor van der Veen; Kaveh Razavi; Onur Mutlu (MICRO, 2021)

A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses. - Lois Orosa 001; Abdullah Giray Yaglikçi; Haocong Luo; Ataberk Olgun; Jisung Park 001; Hasan Hassan; Minesh Patel; Jeremie S. Kim; Onur Mutlu (CoRR, 2021)

Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators. - Syed Mohammad Asad Hassan Jafri; Hasan Hassan; Ahmed Hemani; Onur Mutlu (ACM Trans. Archit. Code Optim., 2021)

Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices. - Abdullah Giray Yaglikçi; Haocong Luo; Geraldo F. de Oliviera; Ataberk Olgun; Minesh Patel; Jisung Park 001; Hasan Hassan; Jeremie S. Kim; Lois Orosa 001; Onur Mutlu (DSN, 2022)

DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators. - F. Nisa Bostanci; Ataberk Olgun; Lois Orosa 001; Abdullah Giray Yaglikçi; Jeremie S. Kim; Hasan Hassan; Oguz Ergin; Onur Mutlu (HPCA, 2022)

PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques. - Ataberk Olgun; Juan Gómez-Luna; Konstantinos Kanellopoulos; Behzad Salami 001; Hasan Hassan; Oguz Ergin; Onur Mutlu (ISVLSI, 2022)

HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips. - Abdullah Giray Yaglikçi; Ataberk Olgun; Minesh Patel; Haocong Luo; Hasan Hassan; Lois Orosa 001; Oguz Ergin; Onur Mutlu (MICRO, 2022)

A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations. - Hasan Hassan; Ataberk Olgun; Abdullah Giray Yaglikçi; Haocong Luo; Onur Mutlu (CoRR, 2022)

Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture. - Ataberk Olgun; F. Nisa Bostanci; Geraldo F. Oliveira; Yahya Can Tugrul; Rahul Bera; Abdullah Giray Yaglikçi; Hasan Hassan; Oguz Ergin; Onur Mutlu (CoRR, 2022)

MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations. - Nandita Vijaykumar; Ataberk Olgun; Konstantinos Kanellopoulos; F. Nisa Bostanci; Hasan Hassan; Mehrshad Lotfi; Phillip B. Gibbons; Onur Mutlu (ACM Trans. Archit. Code Optim., 2022)

Improving DRAM Performance, Reliability, and Security by Rigorously Understanding Intrinsic DRAM Operation. - Hasan Hassan (2022)

Improving DRAM Performance, Reliability, and Security by Rigorously Understanding Intrinsic DRAM Operation. - Hasan Hassan (CoRR, 2023)

PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM. - Ataberk Olgun; Juan Gómez-Luna; Konstantinos Kanellopoulos; Behzad Salami 001; Hasan Hassan; Oguz Ergin; Onur Mutlu (ACM Trans. Archit. Code Optim., 2023)

DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips. - Ataberk Olgun; Hasan Hassan; Abdullah Giray Yaglikçi; Yahya Can Tugrul; Lois Orosa 001; Haocong Luo; Minesh Patel; Oguz Ergin; Onur Mutlu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient DRAM Maintenance Operations. - Hasan Hassan; Ataberk Olgun; A. Giray Yaglikçi; Haocong Luo; Onur Mutlu (MICRO, 2024)

Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture. - Ataberk Olgun; F. Nisa Bostanci; Geraldo Francisco de Oliveira Junior; Yahya Can Tugrul; Rahul Bera; Abdullah Giray Yaglikçi; Hasan Hassan; Oguz Ergin; Onur Mutlu (ACM Trans. Archit. Code Optim., 2024)