APDL: A Processor Description Language For Design Space Exploration of Embedded Processors. - Nima Honarmand; Hasan Sohofi; Maghsoud Abbaspour; Zainalabedin Navabi (FDL, 2007)

High Level Synthesis of Degradable ASICs Using Virtual Binding. - Nima Honarmand; Ali Shahabi; Hasan Sohofi; Maghsoud Abbaspour; Zainalabedin Navabi (VTS, 2007)

Degradable mesh-based on-chip networks using programmable routing tables. - Ali Shahabi; Nima Honarmand; Hasan Sohofi; Zainalabedin Navabi (IEICE Electron. Express, 2007)

A reconfigurable online BIST for combinational hardware using digital neural networks. - S. Behdad Hosseini; Ali Shahabi; Hasan Sohofi; Zainalabedin Navabi (ETS, 2010)

A partitioning approach to improve reconfigurable neuron-inspired online BIST. - Ali Shahabi; S. Behdad Hosseini; Hasan Sohofi; Zainalabedin Navabi (IOLTS, 2010)

Assertion-based verification for system-level designs. - Hasan Sohofi; Zainalabedin Navabi (ISQED, 2014)

Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric. - Nasim Farahini; Ahmed Hemani; Hasan Sohofi; Syed M. A. H. Jafri; Muhammad Adeel Tajammul; Kolin Paul (Microprocess. Microsystems, 2014)

Physical design aware system level synthesis of hardware. - Nasim Farahini; Ahmed Hemani; Hasan Sohofi; Shuo Li 002 (SAMOS, 2015)

System-level assertions: approach for electronic system-level verification. - Hasan Sohofi; Zainalabedin Navabi (IET Comput. Digit. Tech., 2015)