Comparative Evaluation of Adaptive and Deterministic Routing in the OTIS-Hypercube. - Hashem Hashemi Najaf-abadi; Hamid Sarbazi-Azad (Asia-Pacific Computer Systems Architecture Conference, 2004)

A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline. - Hashem Hashemi Najaf-abadi (ASP-DAC, 2004)

An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems. - Hashem Hashemi Najaf-abadi; Hamid Sarbazi-Azad (ICCD, 2004)

Performance Modeling of Fully Adaptive Wormhole Routing in 2-D Mesh-Connected Multiprocessors. - Hashem Hashemi Najaf-abadi; Hamid Sarbazi-Azad; Pedram Rajabzadeh (MASCOTS, 2004)

The Effect of Adaptivity on the Performance of the OTIS-Hypercube Under Different Traffic Patterns. - Hashem Hashemi Najaf-abadi; Hamid Sarbazi-Azad (NPC, 2004)

An Empirical Comparison of OTIS-Mesh and OTIS-Hypercube Multicomputer Systems under Deterministic Routing. - Hashem Hashemi Najaf-abadi; Hamid Sarbazi-Azad (IPDPS, 2005)

Analytic Performance Evaluation of OTIS-Hypercubes. - Hashem Hashemi Najaf-abadi; Hamid Sarbazi-Azad (IEICE Trans. Inf. Syst., 2006)

Multicast communication in OTIS-hypercube multi-computer systems. - Hashem Hashemi Najaf-abadi; Hamid Sarbazi-Azad (Int. J. High Perform. Comput. Netw., 2006)

An empirical performance analysis of minimal and non-minimal routing in cube-based OTIS multicomputers. - Hashem Hashemi Najaf-abadi; Hamid Sarbazi-Azad (J. High Speed Networks, 2007)

Architectural contesting: exposing and exploiting temperamental behavior. - Hashem Hashemi Najaf-abadi; Eric Rotenberg (SIGARCH Comput. Archit. News, 2007)

Configurational Workload Characterization. - Hashem Hashemi Najaf-abadi; Eric Rotenberg (ISPASS, 2008)

Core-Selectability in Chip Multiprocessors. - Hashem Hashemi Najaf-abadi; Niket Kumar Choudhary; Eric Rotenberg (PACT, 2009)

Architectural Contesting. - Hashem Hashemi Najaf-abadi; Eric Rotenberg (HPCA, 2009)

The importance of accurate task arrival characterization in the design of processing cores. - Hashem Hashemi Najaf-abadi; Eric Rotenberg (IISWC, 2009)

Performance modeling of n-dimensional mesh networks. - Pedram Rajabzadeh; Hamid Sarbazi-Azad; Hamid R. Zarandi; Ebrahim Khodaie; Hashem Hashemi Najaf-abadi; Mohamed Ould-Khaoua (Perform. Evaluation, 2010)

FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template. - Niket Kumar Choudhary; Salil V. Wadhavkar; Tanmay A. Shah; Hiran Mayukh; Jayneel Gandhi; Brandon H. Dwiel; Sandeep Navada; Hashem Hashemi Najaf-abadi; Eric Rotenberg (ISCA, 2011)

CRUISE: cache replacement and utility-aware scheduling. - Aamer Jaleel; Hashem Hashemi Najaf-abadi; Samantika Subramaniam; Simon C. Steely Jr.; Joel S. Emer (ASPLOS, 2012)

FabScalar: Automating Superscalar Core Design. - Niket Kumar Choudhary; Salil V. Wadhavkar; Tanmay A. Shah; Hiran Mayukh; Jayneel Gandhi; Brandon H. Dwiel; Sandeep Navada; Hashem Hashemi Najaf-abadi; Eric Rotenberg (IEEE Micro, 2012)