A new compensation technique for two-stage CMOS operational transconductance amplifiers. - Mohammad Yavari; Hashem Zare-Hoseini; M. Farazian; Omid Shoaei (ICECS, 2003)

A very low-noise low-power integrator for high-resolution ΔΣ modulators. - Hashem Zare-Hoseini; Mohammad Yavari; Omid Shoaei (ICECS, 2003)

Design of a 0.8 Volt fully differential CMOS OTA using the bulk-driven technique. - Yasutaka Haga; Hashem Zare-Hoseini; Laurence Berkovi; Izzet Kale (ISCAS (1), 2005)

On the effects of finite and nonlinear DC-gain of the amplifiers in switched-capacitor Delta-Sigma modulators. - Hashem Zare-Hoseini; Izzet Kale (ISCAS (3), 2005)

A new multiply-by-two gain-stage with enhanced immunity to capacitor-mismatch. - Hashem Zare-Hoseini; Omid Shoaei; Izzet Kale (ISCAS (2), 2005)

Modeling of switched-capacitor delta-sigma Modulators in SIMULINK. - Hashem Zare-Hoseini; Izzet Kale; Omid Shoaei (IEEE Trans. Instrum. Meas., 2005)

A Low-Power Highly Linear CMOS Transconductance Topology. - Hashem Zare-Hoseini; Izzet Kale; Richard C. S. Morling (ICECS, 2006)

Continuous time delta sigma modulators with reduced clock jitter sensitivity. - Hashem Zare-Hoseini; Izzet Kale (ISCAS, 2006)

A new structure for capacitor-mismatch-insensitive multiply-by-two amplification. - Hashem Zare-Hoseini; Omid Shoaei; Izzet Kale (ISCAS, 2006)

High power factor wireless power transfer front-end circuit for heterogeneous systems. - Philex Ming-Yan Fan; Hashem Zare-Hoseini; David G. Hasko; Arokia Nathan (MWSCAS, 2017)

A Mismatch Calibration Technique for SAR ADCs Based on Deterministic Self-Calibration and Stochastic Quantization. - Mojtaba Bagheri; Filippo Schembari; Naser Pourmousavian; Hashem Zare-Hoseini; David G. Hasko; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Interchannel Mismatch Calibration Techniques for Time-Interleaved SAR ADCs. - Mojtaba Bagheri; Filippo Schembari; Hashem Zare-Hoseini; Robert Bogdan Staszewski; Arokia Nathan (IEEE Open J. Circuits Syst., 2021)