Design of Artificial Spiking Neuron with SiO2 Memristive Synapse to Demonstrate Neuron-Level Spike Timing Dependent Plasticity. - Jessie Xuhua Niu; Hasita Veluri; Yida Li; Umesh Chand; Jin Feng Leong; Evgeny Zamburg; Maheswari Sivan; Aaron Voon-Yew Thean (ICICDT, 2019)

Quantifying the Benefits of Monolithic 3D Computing Systems Enabled by TFT and RRAM. - Abdallah M. Felfel; Kamalika Datta; Arko Dutt; Hasita Veluri; Ahmed Zaky; Aaron Voon-Yew Thean; Mohamed M. Sabry Aly (DATE, 2020)

High-Throughput, Area-Efficient, and Variation-Tolerant 3-D In-Memory Compute System for Deep Convolutional Neural Networks. - Hasita Veluri; Yida Li; Jessie Xuhua Niu; Evgeny Zamburg; Aaron Voon-Yew Thean (IEEE Internet Things J., 2021)

Sub-10nm Ultra-thin ZnO Channel FET with Record-High 561 µA/µm ION at VDS 1V, High µ-84 cm2/V-s and1T-1RRAM Memory Cell Demonstration Memory Implications for Energy-Efficient Deep-Learning Computing. - Umesh Chand; Mohamed M. Sabry Aly; Manohar Lal; Chen Chun-Kuei; Sonu Hooda; Shih-Hao Tsai; Zihang Fang; Hasita Veluri; Aaron Voon-Yew Thean (VLSI Technology and Circuits, 2022)

A Low-Power DNN Accelerator Enabled by a Novel Staircase RRAM Array. - Hasita Veluri; Umesh Chand; Yida Li; Baoshan Tang; Aaron Voon-Yew Thean (IEEE Trans. Neural Networks Learn. Syst., 2023)

BMX-FPCA: 3D Beyond-Moore Flexible Field Programmable Crossbar Array Architecture. - Hasita Veluri; Dilip Vasudevan (ISQED, 2024)

InFormer: A High-throughput, Ultra-efficient In-memory Compute-based Floating-point Arithmetic Accelerator for Transformers. - Hasita Veluri; Dilip Vasudevan (ACM Great Lakes Symposium on VLSI, 2025)

An Error-Resilient Compute-in-Memory 3D FPCA Architecture for High-Performance Floating-Point Operations. - Hasita Veluri; Dilip Vasudevan (ISQED, 2025)

A Low-Latency DNN Accelerator Enabled by DFT-Based Convolution Execution Within Crossbar Arrays. - Hasita Veluri; Umesh Chand; Chun-Kuei Chen; Aaron Voon-Yew Thean (IEEE Trans. Neural Networks Learn. Syst., 2025)