On the Design of Architectural Pattern to Develop Dynamically Reconfigurable Autonomic Component. - Saeed Parsa; Hassan Daryanavard (NCM (1), 2008)

A Low-Power Improved-Accuracy Approximate Error-Report-Propagate Adder for DSP Applications. - Farshid Ahmadi; Mohammad R. Semati; Hassan Daryanavard (Circuits Syst. Signal Process., 2023)

Energy-efficient approximate full adders for error-tolerant applications. - Farshid Ahmadi; Mohammad R. Semati; Hassan Daryanavard; Atefeh Minaeifar (Comput. Electr. Eng., 2023)

Scalable and custom-precision floating-point hardware convolution core for using in AI edge processors. - Mahdi Shafiei; Hassan Daryanavard; Ahmad Hatam (J. Real Time Image Process., 2023)

High-speed YOLOv4-tiny hardware accelerator for self-driving automotive. - Zahra Valadanzoj; Hassan Daryanavard; Abbas Harifi (J. Supercomput., 2024)

A novel multiplier-less convolution core for YOLO CNN ASIC implementation. - Shoorangiz Bagherzadeh; Hassan Daryanavard; Mohammad R. Semati (J. Real Time Image Process., 2024)

A Hybrid PSO-GA Optimization Method for Relay Node Placement and Connection Point Detection in IoT Applications. - Hassan Daryanavard; Javad Dogani (Trans. Emerg. Telecommun. Technol., 2025)