A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission. - Delong Cui; Bharath Raghavan; Ullas Singh; Anand Vasani; Zhi Chao Huang; Deyi Pi; Mehdi Khanpour; Ali Nazemi; Hassan Maarefi; Tamer A. Ali 001; Nick Huang; Wei Zhang; et al. (ISSCC, 2012)

A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission. - Delong Cui; Bharath Raghavan; Ullas Singh; Anand Vasani; Zhi Chao Huang; Deyi Pi; Mehdi Khanpour; Ali Nazemi; Hassan Maarefi; Wei Zhang; Tamer A. Ali 001; Nick Huang; et al. (IEEE J. Solid State Circuits, 2012)

A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications. - Burak Çatli; Ali Nazemi; Tamer A. Ali 001; Siavash Fallahi; Yang Liu; Jaehyup Kim; Mohammed M. Abdul-Latif; Mahmoud Reza Ahmadi; Hassan Maarefi; Afshin Momtaz; Namik Kocaman (CICC, 2013)

A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS. - Bharath Raghavan; Delong Cui; Ullas Singh; Hassan Maarefi; Dave Pi; Anand Vasani; Zhi Chao Huang; Afshin Momtaz; Jun Cao 001 (ISSCC, 2013)

A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS. - Bharath Raghavan; Delong Cui; Ullas Singh; Hassan Maarefi; Deyi Pi; Anand Vasani; Zhi Chao Huang; Burak Çatli; Afshin Momtaz; Jun Cao 001 (IEEE J. Solid State Circuits, 2013)