A Low-Latency and Low-Complexity Point-Multiplication in ECC. - Raziyeh Salarifard; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Post-Quantum Cryptoprocessors Optimized for Edge and Resource-Constrained Devices in IoT. - Shahriar Ebrahimi; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani (IEEE Internet Things J., 2019)

Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain Over $GF(2^m)$. - Taha Shahroodi; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Implementation of Supersingular Isogeny-Based Diffie-Hellman and Key Encapsulation Using an Efficient Scheduling. - Mohammad Hossein Farzam; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani (IEEE Trans. Circuits Syst., 2020)

A Trusted Design Platform for Trojan Detection in FPGA Bitstreams Using Partial Reconfiguration. - Nastaran Shekofte; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani (ISC Int. J. Inf. Secur., 2021)

Hardware Architecture for Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Fast Montgomery Multiplier. - Mohammad Hossein Farzam; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani; Armin Alivand (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Fast Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Customized Pipelined Montgomery Multiplier. - Mohammad Hossein Farzam; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani; Armin Alivand (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Fixflow: A Framework to Evaluate Fixed-point Arithmetic in Light-Weight CNN Inference. - Farhad Taheri; Siavash Bayat Sarmadi; Hatameh Mosanaei-Boorani; Reza Taheri (CoRR, 2023)

A Digital Signature Architecture Suitable for V2V Applications. - Hatameh Mosanaei-Boorani; Siavash Bayat Sarmadi (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)