A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control. - Hayate Okuhara; Kimiyoshi Usami; Hideharu Amano (COOL Chips, 2015)

7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2. - Koichiro Masuyama; Yu Fujita; Hayate Okuhara; Hideharu Amano (FPL, 2015)

Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB. - Yu Fujita; Hayate Okuhara; Koichiro Masuyama; Hideharu Amano (CANDAR, 2015)

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET. - Hayate Okuhara; Kuniaki Kitamori; Yu Fujita; Kimiyoshi Usami; Hideharu Amano (ISLPED, 2015)

A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2. - Koichiro Masuyama; Yu Fujita; Hayate Okuhara; Hideharu Amano (ReConFig, 2015)

MuCCRA4-BB: A fine-grained body biasing capable DRP. - Johannes Maximilian Kühn; Akram Ben Ahmed; Hayate Okuhara; Hideharu Amano; Oliver Bringmann 001; Wolfgang Rosenstiel (COOL Chips, 2016)

Body bias grain size exploration for a coarse grained reconfigurable accelerator. - Yusuke Matsushita 001; Hayate Okuhara; Koichiro Masuyama; Yu Fujita; Ryuta Kawano; Hideharu Amano (FPL, 2016)

Variable pipeline structure for Coarse Grained Reconfigurable Array CMA. - Naoki Ando; Koichiro Masuyama; Hayate Okuhara; Hideharu Amano (FPT, 2016)

Leveraging asymmetric body bias control for low power LSI design. - Hayate Okuhara; Akram Ben Ahmed; Johannes Maximilian Kühn; Hideharu Amano (COOL Chips, 2017)

Body bias optimization for variable pipelined CGRA. - Takuya Kojima; Naoki Ando; Hayate Okuhara; Ng. Anh Vu Doan; Hideharu Amano (FPL, 2017)

Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA. - Nguyen Anh Vu Doan; Yusuke Matsushita 001; Naoki Ando; Hayate Okuhara; Hideharu Amano (MCSoC, 2017)

Glitch-aware variable pipeline optimization for CGRAs. - Takuya Kojima; Naoki Ando; Hayate Okuhara; Hideharu Amano (ReConFig, 2017)

Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator. - Yusuke Matsushita 001; Hayate Okuhara; Koichiro Masuyama; Yu Fujita; Ryuta Kawano; Hideharu Amano (IEICE Trans. Inf. Syst., 2017)

Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET. - Hayate Okuhara; Yu Fujita; Kimiyoshi Usami; Hideharu Amano (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Design automation methodology of a critical path monitor for adaptive voltage controls. - Ryosuke Kazami; Hayate Okuhara; Hideharu Amano (COOL CHIPS, 2018)

Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping. - Takuya Kojima; Naoki Ando; Yusuke Matshushita; Hayate Okuhara; Ng. Anh Vu Doan; Hideharu Amano (HEART, 2018)

Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. - Akram Ben Ahmed; Hayate Okuhara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (MCSoC, 2018)

Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures. - Takuya Kojima; Naoki Ando; Hayate Okuhara; Ng. Anh Vu Doan; Hideharu Amano (IEICE Trans. Inf. Syst., 2018)

Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach. - Carlos Cesar Cortes Torres; Hayate Okuhara; Nobuyuki Yamasaki; Hideharu Amano (IEICE Trans. Inf. Syst., 2018)

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems. - Hayate Okuhara; Akram Ben Ahmed; Hideharu Amano (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Body Bias Control for Renewable Energy Source with a High Inner Resistance. - Keita Azegami; Hayate Okuhara; Hideharu Amano (IEEE Trans. Multi Scale Comput. Syst., 2018)

Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization. - Hayate Okuhara; Akram Ben Ahmed; Johannes Maximilian Kühn; Hideharu Amano (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process. - Hideto Kayashima; Takuya Kojima; Hayate Okuhara; Tsunaaki Shidei; Hideharu Amano (CANDAR Workshops, 2019)

A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration. - Hayate Okuhara; Ryosuke Kazami; Hideharu Amano (MCSoC, 2019)

A Preliminary Evaluation of Building Block Computing Systems. - Sayaka Terashima; Takuya Kojima; Hayate Okuhara; Kazusa Musha; Hideharu Amano; Ryuichi Sakamoto; Masaaki Kondo; Mitaro Namiki (MCSoC, 2019)

An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes. - Hayate Okuhara; Ahmed Elnaqib; Davide Rossi; Alfio Di Mauro; Philipp Mayer; Pierpaolo Palestri; Luca Benini (ISCAS, 2020)

Flexible Software-Defined Packet Processing Using Low-Area Hardware. - Hesam Zolfaghari; Davide Rossi; Walter Cerroni; Hayate Okuhara; Carla Raffaelli; Jari Nurmi (IEEE Access, 2020)

A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS. - Hayate Okuhara; Ahmed Elnaqib; Martino Dazzi; Pierpaolo Palestri; Simone Benatti; Luca Benini; Davide Rossi (CoRR, 2021)

A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL. - Ahmed Elnaqib; Hayate Okuhara; Taekwang Jang; Davide Rossi; Luca Benini (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS. - Hayate Okuhara; Ahmed Elnaqib; Martino Dazzi; Pierpaolo Palestri; Simone Benatti; Luca Benini; Davide Rossi (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Body Bias Control on a CGRA based on Convex Optimization. - Takuya Kojima; Hayate Okuhara; Masaaki Kondo; Hideharu Amano (COOL CHIPS, 2022)

55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes. - Karim Ali Ahmed; Hayate Okuhara; Massimo Alioto (ISSCC, 2023)

A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Davide Rossi; Gianna Paulin; Angelo Garofalo; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Vincent Huard; Olivier Montfort; Lionel Jure; et al. (ISSCC, 2023)

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Gianna Paulin; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Luca Benini (CoRR, 2023)

A Scalable Body Bias Optimization Method Toward Low-Power CGRAs. - Takuya Kojima; Hayate Okuhara; Masaaki Kondo; Hideharu Amano (IEEE Micro, 2023)

SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. - Takuya Kojima; Yosuke Yanai; Hayate Okuhara; Hideharu Amano; Morihiro Kuga; Masahiro Iida (COOL CHIPS, 2024)

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Gianna Paulin; Angelo Garofalo; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Luca Benini (IEEE J. Solid State Circuits, 2024)