A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement. - Hayato Mashiko; Yukihide Kohira (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Yield and power improvement method by post-silicon delay tuning and technology mapping. - Hayato Mashiko; Yukihide Kohira (APCCAS, 2016)

Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework. - Junki Kawaguchi; Hayato Mashiko; Yukihide Kohira (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Clustering Method for Reduction of Area and Power Consumption on Post-Silicon Delay Tuning. - Kota Muroi; Hayato Mashiko; Yukihide Kohira (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)