An integrated debugging environment for reprogrammble hardware systems. - Kevin Camera; Hayden Kwok-Hay So; Robert W. Brodersen (AADEBUG, 2005)

A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH. - Hayden Kwok-Hay So; Artem Tkachenko; Robert W. Brodersen (CODES+ISSS, 2006)

Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support. - Hayden Kwok-Hay So; Robert W. Brodersen (FPL, 2006)

ASIC Design and Verification in an FPGA Environment. - Dejan Markovic; Chen Chang; Brian C. Richards; Hayden Kwok-Hay So; Borivoje Nikolic; Robert W. Brodersen (CICC, 2007)

Runtime Filesystem Support for Reconfigurable FPGA Hardware Processes in BORPH. - Hayden Kwok-Hay So; Robert W. Brodersen (FCCM, 2008)

Direct sigma-delta modulated signal processing in FPGA. - Chiu-Wah Ng; Ngai Wong 001; Hayden Kwok-Hay So; Tung-Sang Ng (FPL, 2008)

File system access from reconfigurable FPGA hardware processes in BORPH. - Hayden Kwok-Hay So; Robert W. Brodersen (FPL, 2008)

Quad-level bit-stream signal processing on FPGAs. - Chiu-Wah Ng; Ngai Wong 001; Hayden Kwok-Hay So; Tung-Sang Ng (FPT, 2008)

A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH. - Hayden Kwok-Hay So; Robert W. Brodersen (ACM Trans. Embed. Comput. Syst., 2008)

Operation scheduling for FPGA-based reconfigurable computers. - Colin Yu Lin; Ngai Wong 001; Hayden Kwok-Hay So (FPL, 2009)

Design space exploration for sparse matrix-matrix multiplication on FPGAs. - Colin Yu Lin; Zheng Zhang 005; Ngai Wong 001; Hayden Kwok-Hay So (FPT, 2010)

Dynamic power reduction of FPGA-based reconfigurable computers using precomputation. - Chi Chiu Tsang; Hayden Kwok-Hay So (SIGARCH Comput. Archit. News, 2010)

Zero-configuration identity-based IP network encryptor. - Sammy H. M. Kwok; Hayden Kwok-Hay So; Edmund Y. Lam; King-Shan Lui (IEEE Trans. Consumer Electron., 2010)

A Model for Peak Matrix Performance on FPGAs. - Colin Yu Lin; Hayden Kwok-Hay So; Philip Heng Wai Leong (FCCM, 2011)

A Model for Matrix Multiplication Performance on FPGAs. - Colin Yu Lin; Hayden Kwok-Hay So; Philip Heng Wai Leong (FPL, 2011)

On IIR-based bit-stream multipliers. - Chiu-Wah Ng; Ngai Wong 001; Hayden Kwok-Hay So; Tung-Sang Ng (Int. J. Circuit Theory Appl., 2011)

Medical Ultrasound Imaging: To GPU or Not to GPU? - Hayden Kwok-Hay So; Junying Chen; Billy Y. S. Yiu; Alfred C. H. Yu (IEEE Micro, 2011)

Design space exploration of adaptive beamforming acceleration for bedside and portable medical ultrasound imaging. - Junying Chen; Billy Y. S. Yiu; Brandon Kyle Hamilton; Alfred C. H. Yu; Hayden Kwok-Hay So (SIGARCH Comput. Archit. News, 2011)

Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only). - Colin Yu Lin; Ngai Wong 001; Hayden Kwok-Hay So (FPGA, 2012)

Extending BORPH for shared memory reconfigurable computers. - Changqing Xun; Mei Wen; Nan Wu 003; Chunyuan Zhang; Hayden Kwok-Hay So (FPL, 2012)

Design considerations of real-time adaptive beamformer for medical ultrasound research using FPGA and GPU. - Junying Chen; Alfred C. H. Yu; Hayden Kwok-Hay So (FPT, 2012)

Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis. - Colin Yu Lin; Hayden Kwok-Hay So (SIGARCH Comput. Archit. News, 2012)

A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency. - Cheng Liu 008; Colin Yu Lin; Hayden Kwok-Hay So (FCCM, 2013)

Direct virtual memory access from FPGA for high-productivity heterogeneous computing. - Ho-Cheung Ng; Yuk-Ming Choi; Hayden Kwok-Hay So (FPT, 2013)

Design space exploration for sparse matrix-matrix multiplication on FPGAs. - Colin Yu Lin; Ngai Wong 001; Hayden Kwok-Hay So (Int. J. Circuit Theory Appl., 2013)

Map-reduce processing of k-means algorithm with FPGA-accelerated computer cluster. - Yuk-Ming Choi; Hayden Kwok-Hay So (ASAP, 2014)

Scheduling Mixed-Architecture Processes in Tightly Coupled FPGA-CPU Reconfigurable Computers. - Brandon Kyle Hamilton; Michael Inggs; Hayden Kwok-Hay So (FCCM, 2014)

Mixed-architecture process scheduling on tightly coupled reconfigurable computers. - Brandon Kyle Hamilton; Michael Inggs; Hayden Kwok-Hay So (FPL, 2014)

Automatic Soft CGRA Overlay Customization for High-Productivity Nested Loop Acceleration on FPGAs. - Cheng Liu 008; Hayden Kwok-Hay So (FCCM, 2015)

Significant papers from the first 25 years of the FPL conference. - Philip Heng Wai Leong; Hideharu Amano; Jason Helge Anderson; Koen Bertels; João M. P. Cardoso; Oliver Diessel; Guy Gogniat; Mike Hutton; JunKyu Lee; Wayne Luk; Patrick Lysaght; Marco Platzner; et al. (FPL, 2015)

QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay. - Cheng Liu 008; Ho-Cheung Ng; Hayden Kwok-Hay So (FPT, 2015)

Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy. - Junyi Xie; Xinyu Niu; Andy K. S. Lau; Kevin K. Tsia; Hayden Kwok-Hay So (FPT, 2015)

Architecture for Dual-Mode Quadruple Precision Floating Point Adder. - Manish Kumar Jaiswal; B. Sharat Chandra Varma 001; Hayden Kwok-Hay So (ISVLSI, 2015)

Dual-mode double precision / two-parallel single precision floating point multiplier architecture. - Manish Kumar Jaiswal; Hayden Kwok-Hay So (VLSI-SoC, 2015)

Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay. - Cheng Liu 008; Ho-Cheung Ng; Hayden Kwok-Hay So (CoRR, 2015)

Configurable Architectures for Multi-Mode Floating Point Adders. - Manish Kumar Jaiswal; B. Sharat Chandra Varma 001; Hayden Kwok-Hay So; M. Balakrishnan; Kolin Paul; Ray C. C. Cheung (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

FPGA Overlays. - Hayden Kwok-Hay So; Cheng Liu 008 (FPGAs for Software Programmers, 2016)

Architecture for quadruple precision floating point division with multi-precision support. - Manish Kumar Jaiswal; Hayden Kwok-Hay So (ASAP, 2016)

Unsupervised tracking with a low computational cost using the doubly stochastic Dirichlet process mixture model. - Xing Sun 001; Nelson H. C. Yung; Edmund Y. Lam; Hayden K. H. So (Image Processing: Machine Vision Applications, 2016)

Vertex-Centric Graph Processing on FPGA. - Nina Engelhardt; Hayden Kwok-Hay So (FCCM, 2016)

OLAF'16: Second International Workshop on Overlay Architectures for FPGAs. - Hayden Kwok-Hay So; John Wawrzynek (FPGA, 2016)

GraVF: A vertex-centric distributed graph processing framework on FPGAs. - Nina Engelhardt; Hayden Kwok-Hay So (FPL, 2016)

Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. - Maolin Wang 002; Ho-Cheung Ng; Bob M. F. Chung; B. Sharat Chandra Varma 001; Manish Kumar Jaiswal; Kevin K. Tsia; Ho Cheung Shum; Hayden Kwok-Hay So (FPT, 2016)

Sparse Hierarchical Nonparametric Bayesian learning for light field representation and denoising. - Xing Sun 001; Nan Meng; Zhimin Xu; Edmund Y. Lam; Hayden Kwok-Hay So (IJCNN, 2016)

Data-driven light field depth estimation using deep Convolutional Neural Networks. - Xing Sun 001; Zhimin Xu; Nan Meng; Edmund Y. Lam; Hayden Kwok-Hay So (IJCNN, 2016)

Taylor Series Based Architecture for Quadruple Precision Floating Point Division. - Manish Kumar Jaiswal; Hayden Kwok-Hay So (ISVLSI, 2016)

Dual-mode double precision division architecture. - Manish Kumar Jaiswal; Hayden Kwok-Hay So (MWSCAS, 2016)

Towards FPGA-assisted spark: An SVM training acceleration case study. - Sam M. H. Ho; Maolin Wang 002; Ho-Cheung Ng; Hayden Kwok-Hay So (ReConFig, 2016)

High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. - Ho-Cheung Ng; Maolin Wang 002; Bob M. F. Chung; B. Sharat Chandra Varma 001; Manish Kumar Jaiswal; Sam M. H. Ho; Kevin K. Tsia; Ho Cheung Shum; Hayden Kwok-Hay So (ReConFig, 2016)

A Soft Processor Overlay with Tightly-coupled FPGA Accelerator. - Ho-Cheung Ng; Cheng Liu 008; Hayden Kwok-Hay So (CoRR, 2016)

Proceedings of the 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016). - Hayden Kwok-Hay So; John Wawrzynek (CoRR, 2016)

Consistency Analysis for the Doubly Stochastic Dirichlet Process. - Xing Sun 001; Nelson H. C. Yung; Edmund Y. Lam; Hayden Kwok-Hay So (CoRR, 2016)

FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. - Colin Yu Lin; Zhenghong Jiang; Cheng Fu; Hayden Kwok-Hay So; Haigang Yang (SIGARCH Comput. Archit. News, 2016)

A Parameterizable Activation Function Generator for FPGA-Based Neural Network Applications. - Sam M. H. Ho; C.-H. Dominic Hung; Ho-Cheung Ng; Maolin Wang 002; Hayden Kwok-Hay So (FCCM, 2017)

OLAF'17: Third International Workshop on Overlay Architectures for FPGAs. - Hayden Kwok-Hay So; John Wawrzynek (FPGA, 2017)

NnCore: A parameterized non-linear function generator for machine learning applications in FPGAs. - Sam M. H. Ho; Hayden Kwok-Hay So (FPT, 2017)

Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory. - Justin S. J. Wong; Runbin Shi; Maolin Wang 002; Hayden Kwok-Hay So (FPT, 2017)

Towards Flexible Automatic Generation of Graph Processing Gateware. - Nina Engelhardt; Hayden Kwok-Hay So (HEART, 2017)

Computational single-cell classification using deep learning on bright-field and phase images. - Nan Meng; Hayden Kwok-Hay So; Edmund Y. Lam (MVA, 2017)

Proceedings of the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017). - Hayden Kwok-Hay So; John Wawrzynek (CoRR, 2017)

Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division. - Manish Kumar Jaiswal; Hayden Kwok-Hay So (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Computationally Efficient Hyperspectral Data Learning Based on the Doubly Stochastic Dirichlet Process. - Xing Sun 001; Nelson H. C. Yung; Edmund Y. Lam; Hayden Kwok-Hay So (IEEE Trans. Geosci. Remote. Sens., 2017)

The First 25 Years of the FPL Conference: Significant Papers. - Philip Heng Wai Leong; Hideharu Amano; Jason Helge Anderson; Koen Bertels; João M. P. Cardoso; Oliver Diessel; Guy Gogniat; Mike Hutton; JunKyu Lee; Wayne Luk; Patrick Lysaght; Marco Platzner; et al. (ACM Trans. Reconfigurable Technol. Syst., 2017)

Universal number posit arithmetic generator on FPGA. - Manish Kumar Jaiswal; Hayden Kwok-Hay So (DATE, 2018)

Performance-Driven System Generation for Distributed Vertex-Centric Graph Processing on Multi-FPGA Systems. - Nina Engelhardt; C.-H. Dominic Hung; Hayden Kwok-Hay So (FPL, 2018)

Architecture Generator for Type-3 Unum Posit Adder/Subtractor. - Manish Kumar Jaiswal; Hayden Kwok-Hay So (ISCAS, 2018)

Urban Farming in Myanmar: An Experiential Learning Project for Engineering and Science Students from Hong Kong and Myanmar. - Vincent W. L. Tam; Chunkit Chui; Hayden Kwok-Hay So; Nyein Thwe Khaing; Andy Chung To Kong; Subhayan Roy (TALE, 2018)

A Division-Free and Variable-Regularized LMS-Based Generalized Sidelobe Canceller for Adaptive Beamforming and Its Efficient Hardware Realization. - Wei Zhao 027; Jian-Qiang Lin; S. C. Chan 001; Hayden Kwok-Hay So (IEEE Access, 2018)

An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division. - Manish Kumar Jaiswal; Hayden Kwok-Hay So (Circuits Syst. Signal Process., 2018)

Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors. - Hayden Kwok-Hay So; Warren J. Gross (J. Signal Process. Syst., 2018)

Human somatic label-free bright-field cell images. - Nan Meng; Kevin K. Tsia; Hayden Kwok-Hay So (IEEE DataPort, 2018)

E-LSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System. - Runbin Shi; Junjie Liu; Hayden Kwok-Hay So; Shuo Wang 009; Yun Liang 001 (DAC, 2019)

PACoGen: A Hardware Posit Arithmetic Core Generator. - Manish Kumar Jaiswal; Hayden Kwok-Hay So (IEEE Access, 2019)

Computational Light Field Generation Using Deep Nonparametric Bayesian Learning. - Nan Meng; Xing Sun 001; Hayden Kwok-Hay So; Edmund Y. Lam (IEEE Access, 2019)

Design of quadruple precision multiplier architectures with SIMD single and double precision support. - Manish Kumar Jaiswal; Hayden Kwok-Hay So (Integr., 2019)

High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing. - Runbin Shi; Justin S. J. Wong; Hayden Kwok-Hay So (J. Imaging, 2019)

A Real-Time Coprime Line Scan Super-Resolution System for Ultra-Fast Microscopy. - Runbin Shi; Justin S. J. Wong; Edmund Y. Lam; Kevin K. Tsia; Hayden Kwok-Hay So (IEEE Trans. Biomed. Circuits Syst., 2019)

Fringe Pattern Improvement and Super-Resolution Using Deep Learning in Digital Holography. - Zhenbo Ren; Hayden Kwok-Hay So; Edmund Y. Lam (IEEE Trans. Ind. Informatics, 2019)

Large-Scale Multi-Class Image-Based Cell Classification With Deep Learning. - Nan Meng; Edmund Y. Lam; Kevin K. Tsia; Hayden Kwok-Hay So (IEEE J. Biomed. Health Informatics, 2019)

GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms. - Nina Engelhardt; Hayden Kwok-Hay So (ACM Trans. Reconfigurable Technol. Syst., 2019)

FTDL: A Tailored FPGA-Overlay for Deep Learning with High Scalability. - Runbin Shi; Yuhao Ding; Xuechao Wei; He Li 008; Hang Liu 001; Hayden Kwok-Hay So; Caiwen Ding (DAC, 2020)

FTDL: An FPGA-tailored Architecture for Deep Learning Systems. - Runbin Shi; Yuhao Ding; Xuechao Wei; Hang Liu 001; Hayden Kwok-Hay So; Caiwen Ding (FPGA, 2020)

Dynamic Sparse Training: Find Efficient Sparse Network From Scratch With Trainable Masked Layers. - Junjie Liu; Zhe Xu 008; Runbin Shi; Ray C. C. Cheung; Hayden Kwok-Hay So (ICLR, 2020)

Exploiting Elasticity in Tensor Ranks for Compressing Neural Networks. - Jie Ran; Rui Lin; Hayden K. H. So; Graziano Chesi; Ngai Wong 001 (ICPR, 2020)

CSB-RNN: a faster-than-realtime RNN acceleration framework with compressed structured blocks. - Runbin Shi; Peiyan Dong; Tong Geng; Yuhao Ding; Xiaolong Ma; Hayden Kwok-Hay So; Martin C. Herbordt; Ang Li 006; Yanzhi Wang (ICS, 2020)

Vision Guided Crop Detection in Field Robots using FPGA-Based Reconfigurable Computers. - Cyrus Wing-Hei Chan; Philip H. W. Leong; Hayden Kwok-Hay So (ISCAS, 2020)

PARC: ultrafast and accurate clustering of phenotypic data of millions of single cells. - Shobana V. Stassen; Dickson M. D. Siu; Kelvin C. M. Lee; Joshua W. K. Ho; Hayden K. H. So; Kevin K. Tsia (Bioinform., 2020)

HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference. - Zhen Dong 003; Yizhao Gao 002; Qijing Huang 001; John Wawrzynek; Hayden K. H. So; Kurt Keutzer (FCCM, 2021)

Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization Framework. - Sung-En Chang; Yanyu Li; Mengshu Sun; Runbin Shi; Hayden K. H. So; Xuehai Qian; Yanzhi Wang; Xue Lin 001 (HPCA, 2021)

High-Dimensional Dense Residual Convolutional Neural Network for Light Field Reconstruction. - Nan Meng; Hayden K. H. So; Xing Sun 001; Edmund Y. Lam (IEEE Trans. Pattern Anal. Mach. Intell., 2021)

REMOT: A Hardware-Software Architecture for Attention-Guided Multi-Object Tracking with Dynamic Vision Sensors on FPGAs. - Yizhao Gao 002; Song Wang 023; Hayden Kwok-Hay So (FPGA, 2022)

Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network. - Maolin Wang 002; Kelvin C. M. Lee; Bob M. F. Chung; Sharatchandra Varma Bogaraju; Ho-Cheung Ng; Justin S. J. Wong; Ho Cheung Shum; Kevin K. Tsia; Hayden Kwok-Hay So (IEEE Trans. Neural Networks Learn. Syst., 2022)

NITI: Training Integer Neural Networks Using Integer-Only Arithmetic. - Maolin Wang 002; Seyedramin Rasoulinezhad; Philip H. W. Leong; Hayden Kwok-Hay So (IEEE Trans. Parallel Distributed Syst., 2022)

DPACS: Hardware Accelerated Dynamic Neural Network Pruning through Algorithm-Architecture Co-design. - Yizhao Gao 002; Baoheng Zhang; Xiaojuan Qi 001; Hayden Kwok-Hay So (ASPLOS (2), 2023)

MSD: Mixing Signed Digit Representations for Hardware-efficient DNN Acceleration on FPGA with Heterogeneous Resources. - Jiajun Wu 006; Jiajun Zhou; Yizhao Gao 002; Yuhao Ding; Ngai Wong 001; Hayden Kwok-Hay So (FCCM, 2023)

Model-Platform Optimized Deep Neural Network Accelerator Generation through Mixed-Integer Geometric Programming. - Yuhao Ding; Jiajun Wu 006; Yizhao Gao 002; Maolin Wang 002; Hayden Kwok-Hay So (FCCM, 2023)

SqueezeBlock: A Transparent Weight Compression Scheme for Deep Neural Networks. - Mo Song; Jiajun Wu 006; Yuhao Ding; Hayden Kwok-Hay So (ICFPT, 2023)

Towards Asynchronously Triggered Spiking Neural Network on FPGA for Event-based Vision. - Zhenyu Wu; Mo Song; Hayden Kwok-Hay So (ICFPT, 2023)

RSQP: Problem-specific Architectural Customization for Accelerated Convex Quadratic Optimization. - Maolin Wang 002; Ian McInerney; Bartolomeo Stellato; Stephen P. Boyd; Hayden Kwok-Hay So (ISCA, 2023)

Random resistive memory-based deep extreme point learning machine for unified visual processing. - Shaocong Wang; Yizhao Gao 002; Yi Li 049; Woyu Zhang; Yifei Yu; Bo Wang 153; Ning Lin; Hegan Chen; Yue Zhang 011; Yang Jiang; Dingchen Wang; Jia Chen; et al. (CoRR, 2023)

A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking. - Yizhao Gao 002; Song Wang 023; Hayden Kwok-Hay So (ACM Trans. Reconfigurable Technol. Syst., 2023)

Event-Based Eye Tracking. AIS 2024 Challenge Survey. - Zuowen Wang; Chang Gao 002; Zongwei Wu; Marcos V. Conde; Radu Timofte; Shih-Chii Liu; Qinyu Chen; Zhengjun Zha; Wei Zhai; Han Han; Bohao Liao; Yuliang Wu; et al. (CVPR Workshops, 2024)

Co-designing a Sub-millisecond Latency Event-based Eye Tracking System with Submanifold Sparse CNN. - Baoheng Zhang; Yizhao Gao 002; Jingyuan Li; Hayden Kwok-Hay So (CVPR Workshops, 2024)

A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA. - Yizhao Gao 002; Baoheng Zhang; Yuhao Ding; Hayden Kwok-Hay So (FPGA, 2024)

A Case for Low Bitwidth Floating Point Arithmetic on FPGA for Transformer Based DNN Inference. - Jiajun Wu 006; Mo Song; Jingmin Zhao; Hayden Kwok-Hay So (IPDPS (Workshops), 2024)

RAW 2024 Invited Talk-8: Practical Reconfigurable Computing for Next-Generation Edge Applications. - Hayden Kwok-Hay So (IPDPS (Workshops), 2024)

Multi-Issue Butterfly Architecture for Sparse Convex Quadratic Programming. - Maolin Wang 002; Ian McInerney; Bartolomeo Stellato; Fengbin Tu; Stephen P. Boyd; Hayden Kwok-Hay So; Kwang-Ting Cheng (MICRO, 2024)

SeerAttention: Learning Intrinsic Sparse Attention in Your LLMs. - Yizhao Gao 002; Zhichen Zeng 002; Dayou Du; Shijie Cao; Hayden Kwok-Hay So; Ting Cao; Fan Yang 024; Mao Yang 004 (CoRR, 2024)

DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference. - Jiajun Zhou; Jiajun Wu 006; Yizhao Gao 002; Yuhao Ding; Chaofan Tao; Boyu Li; Fengbin Tu; Kwang-Ting Cheng; Hayden Kwok-Hay So; Ngai Wong 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Hardware-Software Design Framework for SpMV Acceleration with Flexible Access Pattern Portfolio. - Zhenyu Wu; Maolin Wang 002; Hayden Kwok-Hay So (HPCA, 2025)

Taijigraph: an Out-Of-Core Graph Processing System Enhanced with Computational Storage. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Hayden Kwok-Hay So; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IPDPS, 2025)

SpikeMOT: Event-Based Multi-Object Tracking With Sparse Motion Features. - Song Wang 023; Zhu Wang; Can Li; Xiaojuan Qi 001; Hayden Kwok-Hay So (IEEE Access, 2025)

TATAA: Programmable Mixed-Precision Transformer Acceleration with a Transformable Arithmetic Architecture. - Jiajun Wu 006; Mo Song; Jingmin Zhao; Yizhao Gao 002; Jia Li; Hayden Kwok-Hay So (ACM Trans. Reconfigurable Technol. Syst., 2025)

SeerAttention-R: Sparse Attention Adaptation for Long Reasoning. - Yizhao Gao 002; Shuming Guo; Shijie Cao; Yuqing Xia; Yu Cheng; Lei Wang 222; Lingxiao Ma; Yutao Sun; Tianzhu Ye; Li Dong 004; Hayden Kwok-Hay So; Yu Hua; et al. (CoRR, 2025)

GuiLoMo: Allocating Expert Number and Rank for LoRA-MoE via Bilevel Optimization with GuidedSelection Vectors. - Hengyuan Zhang; Xinrong Chen; Yingmin Qiu; Xiao Liang; Ziyue Li; Guanyu Wang; Weiping Li; Tong Mo; Wenyue Li; Hayden Kwok-Hay So; Ngai Wong 001 (CoRR, 2025)