Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. - Zied Marrakchi; Hayder Mrabet; Habib Mehrez (ReConFig, 2005)

Implementation of Scalable Embedded FPGA for SOC. - Hayder Mrabet; Zied Marrakchi; Habib Mehrez; André Tissot (ReCoSoC, 2005)

A multilevel hierarchical interconnection structure for FPGA. - Hayder Mrabet; Zied Marrakchi; Pierre Souillot; Habib Mehrez (FPGA, 2006)

Configuration tools for a new multilevel hierarchical FPGA. - Zied Marrakchi; Hayder Mrabet; Habib Mehrez (FPGA, 2006)

Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. - Hayder Mrabet; Zied Marrakchi; Pierre Souillot; Habib Mehrez (ICCAD, 2006)

A new Multilevel Hierarchical MFPGA and its suitable configuration tools. - Zied Marrakchi; Hayder Mrabet; Habib Mehrez (ISVLSI, 2006)

Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. - Hayder Mrabet; Zied Marrakchi; Pierre Souillot; Habib Mehrez; André Tissot (ReCoSoC, 2006)

Efficient Mesh of Tree Interconnect for FPGA Architecture. - Zied Marrakchi; Hayder Mrabet; Christian Masson; Habib Mehrez (FPT, 2007)

Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. - Zied Marrakchi; Hayder Mrabet; Christian Masson; Habib Mehrez (NOCS, 2007)

Efficient tree topology for FPGA interconnect network. - Zied Marrakchi; Hayder Mrabet; Emna Amouri; Habib Mehrez (ACM Great Lakes Symposium on VLSI, 2008)

The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. - Umer Farooq 001; Zied Marrakchi; Hayder Mrabet; Habib Mehrez (ReConFig, 2008)

Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. - Emna Amouri; Hayder Mrabet; Zied Marrakchi; Habib Mehrez (ICECS, 2009)

Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. - Emna Amouri; Hayder Mrabet; Zied Marrakchi; Habib Mehrez (ReConFig, 2009)

FPGA Interconnect Topologies Exploration. - Zied Marrakchi; Hayder Mrabet; Umer Farooq 001; Habib Mehrez (Int. J. Reconfigurable Comput., 2009)

Design and Optimization of Reconfigurable Architectures: The FPGA Family. (Conception et optimisation d'architectures reconfigurables de type FPGA). - Hayder Mrabet (2009)