A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS. - Pier Andrea Francese; Thomas Toifl; Matthias Braendli; Peter Buchmann; Thomas Morf; Marcel A. Kossel; Christian Menolfi; Lukas Kull; Toke Meyer Andersen; Hazar Yueksel (ESSCIRC, 2014)

A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI. - Marcel A. Kossel; Christian Menolfi; Thomas Toifl; Pier Andrea Francese; Matthias Braendli; Thomas Morf; Lukas Kull; Toke Meyer Andersen; Hazar Yueksel (ESSCIRC, 2014)

A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS. - Hazar Yueksel; Lukas Kull; Andreas Burg 001; Matthias Braendli; Peter Buchmann; Pier Andrea Francese; Christian Menolfi; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Danny Luu; Thomas Toifl (ESSCIRC, 2015)

10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver. - Pier Andrea Francese; Thomas Toifl; Matthias Braendli; Christian Menolfi; Marcel A. Kossel; Thomas Morf; Lukas Kull; Toke Meyer Andersen; Hazar Yueksel; Alessandro Cevrero; Danny Luu (ISSCC, 2015)

A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS. - Alessandro Cevrero; Cosimo Aprile; Pier Andrea Francese; Urs Bapst; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Lukas Kull; Hazar Yueksel; Ilter Oezkaya; Yusuf Leblebici; et al. (VLSIC, 2015)

High-speed link with trellis-coded modulation and Reed-Solomon coding. - Hazar Yueksel; Giovanni Cherubini; Roy D. Cideciyan; Simeon Furrer; Andreas Burg 001; Thomas Toifl (CSCN, 2016)

Design considerations for 50G+ backplane links. - Thomas Toifl; Matthias Braendli; Alessandro Cevrero; Pier Andrea Francese; Marcel A. Kossel; Lukas Kull; Danny Luu; Christian Menolfi; Thomas Morf; Ilter Özkaya; Hazar Yueksel (ESSCIRC, 2016)

A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS. - Hazar Yueksel; Matthias Braendli; Andreas Burg 001; Giovanni Cherubini; Roy D. Cideciyan; Pier Andrea Francese; Simeon Furrer; Marcel A. Kossel; Lukas Kull; Danny Luu; Christian Menolfi; Thomas Morf; et al. (ESSCIRC, 2016)

Design considerations on sliding-block viterbi detectors for high-speed data transmission. - Hazar Yueksel; Giovanni Cherubini; Roy D. Cideciyan; Andreas Burg 001; Thomas Toifl (ICSPCS, 2016)

23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path. - Pier Andrea Francese; Matthias Braendli; Christian Menolfi; Marcel A. Kossel; Thomas Morf; Lukas Kull; Alessandro Cevrero; Hazar Yueksel; Ilter Oezkaya; Danny Luu; Thomas Toifl (ISSCC, 2016)

DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology. - Marcel A. Kossel; Christian Menolfi; Pier Andrea Francese; Lukas Kull; Thomas Morf; Thomas Toifl; Matthias Braendli; Alessandro Cevrero; Danny Luu; Ilter Özkaya; Hazar Yueksel (ESSCIRC, 2017)

Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET. - Danny Luu; Lukas Kull; Thomas Toifl; Christian Menolfi; Matthias Braendli; Pier Andrea Francese; Thomas Morf; Marcel A. Kossel; Hazar Yueksel; Alessandro Cevrero; Ilter Özkaya; Qiuting Huang (ESSCIRC, 2017)

28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. - Lukas Kull; Danny Luu; Christian Menolfi; Matthias Braendli; Pier Andrea Francese; Thomas Morf; Marcel A. Kossel; Hazar Yueksel; Alessandro Cevrero; Ilter Özkaya; Thomas Toifl (ISSCC, 2017)

A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET. - Danny Luu; Lukas Kull; Thomas Toifl; Christian Menolfi; Matthias Braendli; Pier Andrea Francese; Thomas Morf; Marcel A. Kossel; Hazar Yueksel; Alessandro Cevrero; Ilter Özkaya; Qiuting Huang (IEEE J. Solid State Circuits, 2018)

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders. - Hazar Yueksel; Matthias Braendli; Andreas Burg 001; Giovanni Cherubini; Roy D. Cideciyan; Pier Andrea Francese; Simeon Furrer; Marcel A. Kossel; Lukas Kull; Danny Luu; Christian Menolfi; Thomas Morf; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Hazar Yueksel; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; et al. (A-SSCC, 2019)

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Hazar Yueksel; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; et al. (ISSCC, 2019)

An Information-Theoretic Perspective on the Relationship Between Fairness and Accuracy. - Sanghamitra Dutta; Dennis Wei; Hazar Yueksel; Pin-Yu Chen; Sijia Liu 001; Kush R. Varshney (CoRR, 2019)

Is There a Trade-Off Between Fairness and Accuracy? A Perspective Using Mismatched Hypothesis Testing. - Sanghamitra Dutta; Dennis Wei; Hazar Yueksel; Pin-Yu Chen; Sijia Liu 001; Kush R. Varshney (ICML, 2020)

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. - Gain Kim; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; Andreas Burg 001; Thomas Toifl; Yusuf Leblebici; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; et al. (IEEE J. Solid State Circuits, 2020)