A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs. - U. Fat Chio; He Gong Wei; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (APCCAS, 2008)

A process- and temperature- insensitive current-controlled delay generator for sampled-data systems. - He Gong Wei; U. Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (APCCAS, 2008)

A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. - Yan Zhu 001; U. Fat Chio; He Gong Wei; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ICECS, 2008)

A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. - He Gong Wei; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2008)

An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. - Sai-Weng Sin; Li Ding; Yan Zhu 001; He Gong Wei; Chi-Hang Chan; U. Fat Chio; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (ESSCIRC, 2010)

An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. - Guohe Yin; U. Fat Chio; He Gong Wei; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Zhihua Wang 001 (ICECS, 2010)

Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC. - U-Fat Chio; He Gong Wei; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS. - He Gong Wei; U-Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. - Yan Zhu 001; U. Fat Chio; He Gong Wei; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (VLSI Design, 2010)

A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. - He Gong Wei; Chi-Hang Chan; U-Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (ISSCC, 2011)

A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS. - Guohe Yin; He Gong Wei; U-Fat Chio; Sai-Weng Sin; Seng-Pan U.; Zhihua Wang 001; Rui Paulo Martins (ESSCIRC, 2012)

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. - He Gong Wei; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2012)

A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration. - Mingqiang Guo; Jiaji Mao; Sai-Weng Sin; He Gong Wei; Rui Paulo Martins (CICC, 2019)

A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing. - Mingqiang Guo; Jiaji Mao; Sai-Weng Sin; He Gong Wei; Rui Paulo Martins (VLSI Circuits, 2019)

A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications. - Mingqiang Guo; Jiaji Mao; Sai-Weng Sin; He Gong Wei; Rui Paulo Martins (IEEE Access, 2020)

A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration. - Mingqiang Guo; Jiaji Mao; Sai-Weng Sin; He Gong Wei; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)