25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV. - Dong-Uk Lee; Kyung Whan Kim; Kwan-Weon Kim; Hongjung Kim; Ju Young Kim; Young Jun Park 006; Jae Hwan Kim; Dae Suk Kim; Heat Bit Park; Jin Wook Shin; Jang Hwan Cho; Ki Hun Kwon; et al. (ISSCC, 2014)

A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control. - Jin-Hee Cho; Jihwan Kim; Wooyoung Lee; Dong-Uk Lee; Tae-Kyun Kim 002; Heat Bit Park; Chunseok Jeong; Myeong-Jae Park; Seung Geun Baek; Seokwoo Choi; Byung Kuk Yoon; Young Jae Choi; et al. (ISSCC, 2018)