A bidirectional lens-free digital-bits-in/-out 0.57mm2 Terahertz nano-radio in CMOS with 49.3mW peak power consumption supporting 50cm Internet-of-Things communication. - Taiyun Chi; Hechen Wang; Min-Yu Huang; Fa Foster Dai; Hua Wang 006 (CICC, 2017)

A 330μW 1.25ps 400fs-INL vernier time-to-digital converter with 2D reconfigurable spiral arbiter array and 2nd-order ΔΣ linearization. - Hechen Wang; Fa Foster Dai; Hua Wang 006 (CICC, 2017)

A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology. - Hechen Wang; Fa Foster Dai (ESSCIRC, 2017)

An 802.11a/b/g/n Digital Fractional-N PLL With Automatic TDC Linearity Calibration for Spur Cancellation. - Dongyi Liao; Hechen Wang; Fa Foster Dai; Yang Xu 017; Roc Berenguer; Sara Munoz Hermoso (IEEE J. Solid State Circuits, 2017)

A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order ΔΣ Linearization. - Hechen Wang; Fa Foster Dai; Hua Wang 006 (IEEE J. Solid State Circuits, 2018)

A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS. - Zhan Su; Hechen Wang; Haoyi Zhao; Zhenqi Chen; Yanjie Wang; Fa Foster Dai (CICC, 2019)

An 8-bit 80-MS/s Fully Self-Timed SAR ADC with 3/2 Interleaved Comparators and High-Order PVT Stabilized HBT Bandgap Reference. - Zhan Su; Hechen Wang; Haoyi Zhao; Xiao Liu; Fa Foster Dai (ISCAS, 2019)

Can a Conversation Paint a Picture? Mining Requirements In Software Forums. - James Tizard; Hechen Wang; Lydia Yohannes; Kelly Blincoe (RE, 2019)

A 3.8 mW Sub-Sampling Direct RF-to-Digital Converter for Polar Receiver Achieving 1.94 Gb/s Data Rate with 1024-APSK Modulation. - Hechen Wang; Zhan Su; Haoyi Zhao; Yanjie Wang; Fa Foster Dai (VLSI Circuits, 2019)

A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs. - Richard Dorrance; Andrey Belogolovy; Hechen Wang; Xue Zhang (FPL, 2020)

Sub-Sampling Direct RF-to-Digital Converter With 1024-APSK Modulation for High Throughput Polar Receiver. - Hechen Wang; Fa Foster Dai; Zhan Su; Yanjie Wang (IEEE J. Solid State Circuits, 2020)

The Use of Sub-forums in Software Product Forums. - Hechen Wang; Peter Devine; James Tizard; Seyed Reza Shahamiri; Kelly Blincoe (RE Workshops, 2021)

What's Inside a Cluster of Software User Feedback: A Study of Characterisation Methods. - Peter Devine; James Tizard; Hechen Wang; Yun Sing Koh; Kelly Blincoe (RE, 2022)

A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference. - Hechen Wang; Renzhi Liu; Richard Dorrance; Deepak Dasalukunte; Xiaosen Liu; Dan Lake; Brent R. Carlton; May Wu (VLSI Technology and Circuits, 2022)

A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference. - Hechen Wang; Renzhi Liu; Richard Dorrance; Deepak Dasalukunte; Dan Lake; Brent R. Carlton (IEEE J. Solid State Circuits, 2023)

A Software Requirements Ecosystem: Linking Forum, Issue Tracker, and FAQs for Requirements Management. - James Tizard; Peter Devine; Hechen Wang; Kelly Blincoe (IEEE Trans. Software Eng., 2023)

An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET. - Richard Dorrance; Deepak Dasalukunte; Hechen Wang; Renzhi Liu; Brent R. Carlton (IEEE J. Solid State Circuits, 2023)

A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications. - Hechen Wang; Renzhi Liu; Richard Dorrance; Deepak Dasalukunte; Niranjan Gowda; Brent R. Carlton (VLSI Technology and Circuits, 2024)

Conversation in forums: How software forum posts discuss potential development insights. - Hechen Wang; Peter Devine; James Tizard; Seyed Reza Shahamiri; Kelly Blincoe (J. Syst. Softw., 2024)