RTD-based compact programmable gates. - José M. Quintana; Maria J. Avedillo; Héctor Pettenghi (IJCNN, 2004)

Programmable logic gate based on resonant tunnelling devices. - José M. Quintana; Maria J. Avedillo; Héctor Pettenghi (ISCAS (3), 2004)

Logic Models Supporting the Design of MOBILE-based RTD Circuits. - Maria J. Avedillo; José M. Quintana; Héctor Pettenghi (ASAP, 2005)

Self-latching operation limits for MOBILE circuits. - José M. Quintana; Maria J. Avedillo; Héctor Pettenghi (ISCAS, 2006)

Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors. - Maria J. Avedillo; José M. Quintana; Héctor Pettenghi Roldán (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Non Return Mobile Logic Family. - Héctor Pettenghi; Maria J. Avedillo; José M. Quintana (ISCAS, 2007)

A novel contribution to the RTD-based threshold logic family. - Héctor Pettenghi; Maria J. Avedillo; José M. Quintana (ISCAS, 2008)

Using multi-threshold threshold gates in RTD-based logic design: A case study. - Héctor Pettenghi; Maria J. Avedillo; José M. Quintana (Microelectron. J., 2008)

Operation Limits for RTD-Based MOBILE Circuits. - José M. Quintana; Maria J. Avedillo; Juan Núñez 002; Héctor Pettenghi (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

An improved RNS generator 2n +/- k based on threshold logic. - Héctor Pettenghi; Ricardo Chaves; Leonel Sousa; Maria J. Avedillo (VLSI-SoC, 2010)

Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion. - Héctor Pettenghi; Leonel Sousa; Jude Angelo Ambrose (ASP-DAC, 2012)

RNS Arithmetic Units for Modulo {2^n+-k}. - Pedro Miguens Matutino; Héctor Pettenghi; Ricardo Chaves; Leonel Sousa (DSD, 2012)

DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks. - Jude Angelo Ambrose; Héctor Pettenghi; Leonel Sousa (ASP-DAC, 2013)

Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks. - Jude Angelo Ambrose; Héctor Pettenghi; Darshana Jayasinghe; Leonel Sousa (IET Circuits Devices Syst., 2013)

RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to (8n+1)-bit. - Héctor Pettenghi; Ricardo Chaves; Leonel Sousa (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Method to Design General RNS Reverse Converters for Extended Moduli Sets. - Héctor Pettenghi; Ricardo Chaves; Leonel Sousa (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Method for designing multi-channel RNS architectures to prevent power analysis SCA. - Héctor Pettenghi; Jude Angelo Ambrose; Ricardo Chaves; Leonel Sousa (ISCAS, 2014)

Method for Designing Efficient Mixed Radix Multipliers. - Héctor Pettenghi; Frederico Pratas; Leonel Sousa (Circuits Syst. Signal Process., 2014)

Efficient Method for Designing Modulo {2n ± k} Multipliers. - Héctor Pettenghi; Sorin Cotofana; Leonel Sousa (J. Circuits Syst. Comput., 2014)

RNS reverse converters based on the new Chinese Remainder Theorem I. - Héctor Pettenghi; Leonel Sousa (ISCAS, 2015)

RNS reverse converters for moduli sets with dynamic ranges of 9n-bit. - Héctor Pettenghi; Roberto de Matos; Amir Sabbagh Molahosseini (LASCAS, 2016)

Method for designing two levels RNS reverse converters for large dynamic ranges. - Héctor Pettenghi; Ricardo Chaves; Roberto de Matos; Leonel Sousa (Integr., 2016)

Efficient implementation of modular multiplication by constants applied to RNS reverse converters. - Roberto de Matos; Rogerio Paludo; Nikolay I. Chervyakov; Pavel Alekseevich Lyakhov; Héctor Pettenghi (ISCAS, 2017)

Efficient RNS Reverse Converters for Moduli Sets with Dynamic Ranges Up to ((10n+1) ) -bit. - Héctor Pettenghi; Rogerio Paludo; Roberto de Matos; Pavel Alekseevich Lyakhov (Circuits Syst. Signal Process., 2018)

Introducing Asymmetry in a CMOS Latch to Obtain Inherent Power-On-Reset Behavior. - Fabián Leonardo Cabrera; Fernando Rangel de Sousa; Héctor Pettenghi (LASCAS, 2019)

Towards the Integration of Reverse Converters into the RNS Channels. - Leonel Sousa; Rogerio Paludo; Paulo Martins 002; Héctor Pettenghi (IEEE Trans. Computers, 2020)

RNS processor using moduli sets of the form 2n±1. - Vanessa Prediger; Fábio Bairros; Laio Oriel Seman; Eduardo Augusto Bezerra; Héctor Pettenghi (Int. J. Circuit Theory Appl., 2023)

A Comprehensive Approach and Analysis of Reverse Converters for a Class of Moduli Sets. - Gabriel Fernandes; Augusto Vassoler; Eduardo Bezerra 001; Leonel Sousa; Héctor Pettenghi (LASCAS, 2024)