A ±25 ps jitter 1.9 V CMOS PLL for UltraSPARC microprocessor. - Hee-Tae Ahn (CICC, 1999)

A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications. - Hee-Tae Ahn; David J. Allstot (IEEE J. Solid State Circuits, 2000)

A 0.5-8.5 GHz fully differential CMOS distributed amplifier. - Hee-Tae Ahn; David J. Allstot (IEEE J. Solid State Circuits, 2002)

A noise optimization technique for integrated low-noise amplifiers. - Jung-Suk Goo; Hee-Tae Ahn; Donald J. Ladwig; Zhiping Yu; Thomas H. Lee; Robert W. Dutton (IEEE J. Solid State Circuits, 2002)

A Phase Noise Optimized 4 GHz Differential Colpitts VCO. - Hee-Tae Ahn; Jinwook Burm (IEICE Trans. Electron., 2010)