Process variation tolerant all-digital multiphase DLL for DDR3 interface. - Heechai Kang; Kyungho Ryu; Donghwan Lee; Won Lee; SuHo Kim; JongRyun Choi; Seong-Ook Jung (CICC, 2010)

Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface. - Heechai Kang; Kyungho Ryu; Dong-Hoon Jung; Donghwan Lee; Won Lee; SuHo Kim; JongRyun Choi; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory. - Heechai Kang; Jisu Kim; Hanwool Jeong; Younghwi Yang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs. - Jung-Hyun Park; Heechai Kang; Dong-Hoon Jung; Kyungho Ryu; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Wideband Receiver Employing PWM-Based Harmonic Rejection Downconversion. - Heechai Kang; Wei-Gi Ho; Vineet Kumar Singh; Ranjit Gharpurey (IEEE J. Solid State Circuits, 2018)

An N-Path Filter with Multiphase PWM Clocks for Harmonic Response Suppression. - Venkata Suresh Rayudu; Heechai Kang; Ranjit Gharpurey (LASCAS, 2020)