Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees. - Heechun Park; Taewhan Kim 001 (ICCAD, 2013)

Synthesis of TSV Fault-Tolerant 3-D Clock Trees. - Heechun Park; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Synthesizing Asynchronous Circuits toward Practical Use. - Heechun Park; Taewhan Kim 001 (ISVLSI, 2016)

Structure optimizations of neuromorphic computing architectures for deep neural network. - Heechun Park; Taewhan Kim 001 (DATE, 2018)

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse. - Jinwoo Kim; Gauthaman Murali; Heechun Park; Eric Qin 001; Hyoukjun Kwon; Venkata Chaitanya Krishna Chekuri; Nihar Dasari; Arvind Singh; Minah Lee; Hakki Mert Torun; Kallol Roy; Madhavan Swaminathan; et al. (DAC, 2019)

RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs. - Heechun Park; Kyungwook Chang; Bon Woong Ku; Jinwoo Kim; Edward Lee; Daehyun Kim 002; Arjun Chaudhuri; Sanmitra Banerjee; Saibal Mukhopadhyay; Krishnendu Chakrabarty; Sung Kyu Lim (DAC, 2019)

Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs. - Arjun Chaudhuri; Sanmitra Banerjee; Heechun Park; Bon Woong Ku; Krishnendu Chakrabarty; Sung Kyu Lim (ETS, 2019)

Hybrid asynchronous circuit generation amenable to conventional EDA flow. - Heechun Park; Taewhan Kim 001 (Integr., 2019)

Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs. - Heechun Park; Bon Woong Ku; Kyungwook Chang; Da Eun Shim; Sung Kyu Lim (ISPD, 2020)

Advances in Design and Test of Monolithic 3-D ICs. - Arjun Chaudhuri; Sanmitra Banerjee; Heechun Park; Jinwoo Kim; Gauthaman Murali; Edward Lee; Daehyun Kim 002; Sung Kyu Lim; Saibal Mukhopadhyay; Krishnendu Chakrabarty (IEEE Des. Test, 2020)

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse. - Jinwoo Kim; Gauthaman Murali; Heechun Park; Eric Qin 001; Hyoukjun Kwon; Venkata Chaitanya Krishna Chekuri; Nael Mizanur Rahman; Nihar Dasari; Arvind Singh; Minah Lee; Hakki Mert Torun; Kallol Roy; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis. - Seyoung Kim; Heechun Park; Jaeha Kim (ISOCC, 2021)

Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology. - Heechun Park; Kyungjoon Chang; Jooyeon Jeong; Jaehoon Ahn; Ki-Seok Chung; Taewhan Kim 001 (ISOCC, 2021)

Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement. - Eunsol Jeong; Heechun Park; Jooyeon Jeong; Taewhan Kim 001 (MWSCAS, 2021)

Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements. - Heechun Park; Bon Woong Ku; Kyungwook Chang; Da Eun Shim; Sung Kyu Lim (ACM Trans. Design Autom. Electr. Syst., 2021)

Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach. - Taehwan Kim 007; Heechun Park; Taewhan Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems. - Gauthaman Murali; Heechun Park; Eric Qin 001; Hakki Mert Torun; Majid Ahadi Dolatsara; Madhavan Swaminathan; Tushar Krishna; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A Systematic Removal of Minimum Implant Area Violations under Timing Constraint. - Eunsol Jeong; Heechun Park; Taewhan Kim 001 (DATE, 2022)

Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. - Suwan Kim; Sehyeon Chung; Taewhan Kim 001; Heechun Park (ISLPED, 2022)

Speeding-up neuromorphic computation for neural networks: Structure optimization approach. - Heechun Park; Taewhan Kim 001 (Integr., 2022)

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs. - Arjun Chaudhuri; Sanmitra Banerjee; Jinwoo Kim; Heechun Park; Bon Woong Ku; Sukeshwar Kannan; Krishnendu Chakrabarty; Sung Kyu Lim (ACM J. Emerg. Technol. Comput. Syst., 2022)

DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. - Kyungjoon Chang; Jaehoon Ahn; Heechun Park; Kyu-Myung Choi; Taewhan Kim 001 (DATE, 2023)

Eliminating Minimum Implant Area Violations With Design Quality Preservation. - Eunsol Jeong; Taewhan Kim 001; Heechun Park (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Timing-Aware Tier Partitioning for 3D ICs with Critical Path Consideration. - Sojung Park; Heechun Park (ICEIC, 2024)

Memristive Logic-in-Memory Implementation with Area Efficiency and Parallelism. - Ikkyum Kim; Heechun Park (ICCD, 2024)

3T1R Memristor Crossbar Architecture for Diverse Logic Implementation. - Ikkyum Kim; Heechun Park (ISOCC, 2024)

Double-Row Flip-flop Design Under Advanced Technology and Its IC-Level Effects. - Yoonjae Lee; Heechun Park (ISOCC, 2024)

Graph Neural Network-Based Detailed Placement Optimization Framework. - Dho Ui Lim; Heechun Park (ISQED, 2024)

Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations. - Junghyun Yoon; Heechun Park (ISQED, 2024)

Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICs. - Suwan Kim; Heechun Park (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement. - Jaehoon Ahn; Kyungjoon Chang; Kyumyung Choi; Taewhan Kim 001; Heechun Park (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation. - Eunsol Jeong; Taewhan Kim 001; Heechun Park (ASP-DAC, 2025)

Clustering-Driven Bonding Terminal Legalization with Reinforcement Learning for F2F 3D ICs. - Gyumin Kim; Heechun Park (ASP-DAC, 2025)

Timing-Driven Detailed Placement with Unsupervised Graph Learning. - Dhoui Lim; Heechun Park (DATE, 2025)