A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core. - Heein Yoon; Yongsun Lee; Jae Joon Kim; Jaehyouk Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A PVT-robust -59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop. - Yongsun Lee; Heein Yoon; Mina Kim; Jaehyouk Choi (VLSI Circuits, 2016)

A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers. - Heein Yoon; Yongsun Lee; Younghyun Lim; Geum-Young Tak; Hong-Teuk Kim; Yo-Chuol Ho; Jaehyouk Choi (IEEE J. Solid State Circuits, 2016)

An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration. - Suneui Park; Heein Yoon; Jaehyouk Choi (A-SSCC, 2017)

19.2 A PVT-robust -39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceivers. - Seyeon Yoo; Seojin Choi; Juyeop Kim; Heein Yoon; Yongsun Lee; Jaehyouk Choi (ISSCC, 2017)

Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers. - Seyeon Yoo; Seojin Choi; Juyeop Kim; Heein Yoon; Yongsun Lee; Jaehyouk Choi (ASP-DAC, 2018)

A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers. - Heein Yoon; Juyeop Kim; Suneui Park; Younghyun Lim; Yongsun Lee; Jooeun Bang; Kyoohyun Lim; Jaehyouk Choi (ISSCC, 2018)

A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers. - Seyeon Yoo; Seojin Choi; Juyeop Kim; Heein Yoon; Yongsun Lee; Jaehyouk Choi (IEEE J. Solid State Circuits, 2018)

A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization. - Juyeop Kim; Heein Yoon; Younghyun Lim; Yongsun Lee; Yoonseo Cho; Taeho Seong; Jaehyouk Choi (ISSCC, 2019)

An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators. - Juyeop Kim; Younghyun Lim; Heein Yoon; Yongsun Lee; Hangi Park; Yoonseo Cho; Taeho Seong; Jaehyouk Choi (IEEE J. Solid State Circuits, 2019)

A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration. - Heein Yoon; Suneui Park; Jaehyouk Choi (IEEE J. Solid State Circuits, 2019)

17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator. - Younghyun Lim; Juyeop Kim; Yongwoo Jo; Jooeun Bang; Seyeon Yoo; Hangi Park; Heein Yoon; Jaehyouk Choi (ISSCC, 2020)

An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS. - Seyeon Yoo; Suneui Park; Seojin Choi; Yoonseo Cho; Heein Yoon; Chanwoong Hwang; Jaehyouk Choi (ISSCC, 2021)

An Area-Efficient CMOS Cross-Coupled LC-VCO Using Nested Intertwined Tail Inductors. - Hyogyoung An; Hyeonjun Nam; Sungjin Kim; Younghyun Lim; Heein Yoon (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Low-Jitter and Wide-Frequency-Range D-Band Frequency Synthesizer With a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier. - Seohee Jung; Jaeho Kim; Jooeun Bang; Sarang Lee; Heein Yoon; Jaehyouk Choi (IEEE J. Solid State Circuits, 2025)