A Low-Power 20 Gbps Multi-phase MDLL-based Digital CDR with Receiver Equalization. - Heejae Hwang; Jongsun Kim (ISOCC, 2019)

A 0.8-3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links. - Heejae Hwang; Jongsun Kim (IEICE Electron. Express, 2019)