A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines. - Nan Xing; Heesoo Song; Deog-Kyoon Jeong; Suhwan Kim 001 (SoCC, 2009)

A 0.3-1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller. - Deok-Soo Kim; Heesoo Song; Taeho Kim; Suhwan Kim 001; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2010)

A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit. - Sungchun Jang; Heesoo Song; Seokmin Ye; Deog-Kyoon Jeong (ISSCC, 2011)

A 1.0-4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control. - Heesoo Song; Deok-Soo Kim; Do-Hwan Oh; Suhwan Kim 001; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2011)