Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology. - Heiner Bauer; Sebastian Höppner; Johannes Partzsch; Dennis Walter; Christian Mayr 001; Florian Schraut; Holger Eisenreich (NORCAS, 2017)

How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC. - Sebastian Höppner; Jörg Schreiter; Robert Niebsch; Stephan Scherzer; Ulrich Hensel; Jörg Winkler; Mario Orgis; Holger Eisenreich; Dennis Walter; Uwe Steeb; André Scharfe; Clifford Dmello; et al. (ESSDERC, 2019)

Hard Real-Time Capable OPC UA Server as Hardware Peripheral for Single Chip IoT Systems. - Chris Paul Iatrou; Heiner Bauer; Markus Graube; Sebastian Höppner; Julian Rahm; Leon Urbas (ETFA, 2019)

A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. - Dennis Walter; André Scharfe; Alexander Oefelein; Florian Schraut; Heiner Bauer; Farkas Csaszar; Robert Niebsch; Jörg Schreiter; Holger Eisenreich; Sebastian Höppner (COOL CHIPS, 2020)

Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology. - Sebastian Höppner; Holger Eisenreich; Dennis Walter; André Scharfe; Alexander Oefelein; Florian Schraut; Jörg Schreiter; Thorsten Riedel; Heiner Bauer; Robert Niebsch; Stephan Scherzer; Thomas Hocker; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Opportunities For A Hardware-Based OPC UA Server Implementation In Industry 4.0. - Zohra Charania; Chris Paul Iatrou; Valentin Khaydarov; Richard Jacob; Robert Wittig; Heiner Bauer; Sebastian Höppner; René Bachmann; Philipp Bauer; Hendrik Deckert; Christian Mayr 001; Gerhard P. Fettweis; et al. (IECON, 2021)

Hardware Implementation of an OPC UA Server for Industrial Field Devices. - Heiner Bauer; Sebastian Höppner; Chris Paul Iatrou; Zohra Charania; Stephan Hartmann 002; Saif-Ur Rehman; Andreas Dixius; Georg Ellguth; Dennis Walter; Johannes Uhlig; Felix Neumärker; Marc Berthel; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 16-Channel Fully Configurable Neural SoC With 1.52 $ mu$W/Ch Signal Acquisition, 2.79 $ mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI. - Seyed Mohammad Ali Zeinolabedin; Franz Marcus Schüffny; Richard George 001; Florian Kelber; Heiner Bauer; Stefan Scholze; Stefan Hänzsche; Marco Stolba; Andreas Dixius; Georg Ellguth; Dennis Walter; Sebastian Höppner; et al. (IEEE Trans. Biomed. Circuits Syst., 2022)

A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power. - Hector A. Gonzalez; Bernhard Vogginger; Chen Liu 031; Marco Stolba; Florian Kelber; Heiner Bauer; Stefan Hänzsche; Stefan Scholze; Marc Berthel; Tim Rosmeisl; Liyuan Guo; Dennis Walter; et al. (CICC, 2023)

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. - Heiner Bauer; Marco Stolba; Stefan Scholze; Dennis Walter; Christian Mayr 001; Alexander Oefelein; Sebastian Höppner; André Scharfe; Florian Schraut; Holger Eisenreich (ISOCC, 2023)

NLU: An Adaptive, Small-Footprint, Low-Power Neural Learning Unit for Edge and IoT Applications. - Amirhossein Rostami; Seyed Mohammad Ali Zeinolabedin; Liyuan Guo; Florian Kelber; Heiner Bauer; Andreas Dixius; Stefan Scholze; Marc Berthel; Dennis Walter; Johannes Uhlig; Bernhard Vogginger; Christian Mayr 001 (IEEE Open J. Circuits Syst., 2025)