A configurable convolution chip with programmable coefficients. - Dirk Reuver; Heinrich Klar (IEEE J. Solid State Circuits, 1992)

Self-Timed Fully Pipelined Multipliers. - O. Salomon; Heinrich Klar (Asynchronous Design Methodologies, 1993)

Design of a general-purpose neural signal processor. - Jörg Beichter; Nico Brüls; Elisabeth Sicheneder; Ulrich Ramacher; Heinrich Klar (Neurocomputing, 1993)

A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters. - S. R. Kadivar; Doris Schmitt-Landsiedel; Heinrich Klar (ICCAD, 1995)

Hardware Requirements for Spike-Processing Neural Networks. - Ulrich Roth; Axel Jahnke; Heinrich Klar (IWANN, 1995)

Calculation of the soft error rate of submicron CMOS logic circuits. - T. Juhnke; Heinrich Klar (IEEE J. Solid State Circuits, 1995)

General algorithms for a simplified addition of 2's complement numbers. - O. Salomon; Jorg-Michael Green; Heinrich Klar (IEEE J. Solid State Circuits, 1995)

A CMOS gate array architecture for digital signal processing applications. - Jorg-Michael Green; Heinrich Klar (IEEE J. Solid State Circuits, 1996)

Simulation of Spiking Neural Networks on Different Hardware Platforms. - Axel Jahnke; Tim Schönauer; Ulrich Roth; K. Mohraz; Heinrich Klar (ICANN, 1997)

On-Line Hebbian Learning for Spiking Neurons: Architecture of the Weight-Unit of NESPINN. - Ulrich Roth; Axel Jahnke; Heinrich Klar (ICANN, 1997)

An Improved Multiplexed Resistive Network for Analog Image Preprocessing. - Chang-Han Yi; Robert Schlabbach; Holger Kroth; Heinrich Klar (ICANN, 1997)

Dynamic Path Planning with Spiking Neural Networks. - Ulrich Roth; Marc Walker; Arne Hilmann; Heinrich Klar (IWANN, 1997)

A New Bio-inspired Algorithm for Early Vision Edge Detection and Image Segmentation. - Chang-Han Yi; Robert Schlabbach; Holger Kroth; Heinrich Klar (IWANN, 1997)

A 12-bit medium-time analog storage device in a CMOS standard process. - Martin Ehlert; Heinrich Klar (IEEE J. Solid State Circuits, 1998)

Simulation of a Digital Neuro-Chip for Spiking Neural Networks. - Tim Schönauer; Sahin Atasoy; Nasser Mehrtash; Heinrich Klar (IJCNN (4), 2000)

Simulation of spiking neural networks – architectures and implementations. - Martin Schäfer; Tim Schönauer; Carsten Wolff; Georg Hartmann; Heinrich Klar; Ulrich Rückert 001 (Neurocomputing, 2002)

NeuroPipe-Chip: A digital neuro-processor for spiking neural networks. - Tim Schönauer; Sahin Atasoy; Nasser Mehrtash; Heinrich Klar (IEEE Trans. Neural Networks, 2002)

Image preprocessing with dynamic synapses. - Nasser Mehrtash; Dietmar Jung; Heinrich Klar (Neural Comput. Appl., 2003)

Synaptic plasticity in spiking neural networks (SP2INN): a system approach. - Nasser Mehrtash; Dietmar Jung; Heik Heinrich Hellmich; Tim Schönauer; Vi Thanh Lu; Heinrich Klar (IEEE Trans. Neural Networks, 2003)

A novel broadband cascade sigma-delta analog-to-digital converter. - Yi Yin; Heinrich Klar; Peter Wennekers (Circuits, Signals, and Systems, 2004)

Emulation engine for spiking neurons and adaptive synaptic weights. - Heik Heinrich Hellmich; M. Geike; P. Griep; Phil Mahr; Marco Rafanelli; Heinrich Klar (IJCNN, 2005)

A cascade 3-1-1 multibit ΣΔ A/D modulator with reduced sensitivity to non-idealities. - Yi Yin; Heinrich Klar; Peter Wennekers (ISCAS (4), 2005)

Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nm. - Adel Fatemi; Heinrich Klar; Friedel Gerfers (ISCAS, 2016)