Nonlinear Analysis of Correlative Tracking Systems Using Renewal Process Theory. - Heinrich Meyr (IEEE Trans. Commun., 1975)

Delay-Lock Tracking of Stochastic Signals. - Heinrich Meyr (IEEE Trans. Commun., 1976)

Complete statistical description of the phase-error process generated by correlative tracking systems. - William C. Lindsey; Heinrich Meyr (IEEE Trans. Inf. Theory, 1977)

Theory of phase tracking systems of arbitrary order: Statistics of cycle slips and probability distribution of the state vector. - Dietrich Ryter; Heinrich Meyr (IEEE Trans. Inf. Theory, 1978)

Phase Acquisition Statistics for Phase-Locked Loops. - Heinrich Meyr; Luitjens Popken (IEEE Trans. Commun., 1980)

Real-time estimation of moving time delay. - Heinrich Meyr; Gerhard Spies; Jörg Bohmann (ICASSP, 1982)

Cycle Slips in Phase-Locked Loops: A Tutorial Survey. - Gerd Ascheid; Heinrich Meyr (IEEE Trans. Commun., 1982)

Transmission Design Criteria for a Synchronous Token Ring. - Heinz J. Keller; Heinrich Meyr; Hans R. Müller (IEEE J. Sel. Areas Commun., 1983)

Performance Analysis for General PN-Spread-Spectrum Acquisition Techniques. - Heinrich Meyr; Gerhard Polzer (IEEE Trans. Commun., 1983)

Synchronization Failures in a Chain of PLL Synchronizers. - Heinrich Meyr; Luitjens Popken; Hans R. Müller (IEEE Trans. Commun., 1986)

An all-digital realization of a baseband DLL implemented as a dynamical state estimator. - Jörg Bohmann; Heinrich Meyr (IEEE Trans. Acoust. Speech Signal Process., 1986)

A Simple Method for Evaluating the Probability Density Function of the Sample Number for the Optimum Sequential Detector. - Heinrich Meyr; Gerhard Polzer (IEEE Trans. Commun., 1987)

Error handling performance of a token ring LAN. - Jürgen Tusch; Heinrich Meyr; Erwin A. Zurfluh (LCN, 1988)

Cycle slips in synchronizers subject to smooth narrow-band loop noise. - Marc Moeneclaey; Stanislaw Starzak; Heinrich Meyr (IEEE Trans. Commun., 1988)

Digital filter and square timing recovery. - Martin Oerder; Heinrich Meyr (IEEE Trans. Commun., 1988)

Transit-time estimation in turbulent flows. - Rolf Peters; Frank Blischke; Heinrich Meyr (IEEE Trans. Acoust. Speech Signal Process., 1988)

Adaptive synchronization and channel parameter estimation using an extended Kalman filter. - Abbas Aghamohammadi; Heinrich Meyr; Gerd Ascheid (IEEE Trans. Commun., 1989)

An all digital receiver architecture for bandwidth efficient transmission at high data rates. - Gerd Ascheid; Martin Oerder; Johannes Stahl 001; Heinrich Meyr (IEEE Trans. Commun., 1989)

Parallel Viterbi algorithm implementation: breaking the ACS-bottleneck. - Gerhard P. Fettweis; Heinrich Meyr (IEEE Trans. Commun., 1989)

A systematic approach to carrier recovery and detection of digitally phase modulated signals of fading channels. - Reinhold Haeb; Heinrich Meyr (IEEE Trans. Commun., 1989)

High-Rate Viterbi Processor: A Systolic Array Solution. - Gerhard P. Fettweis; Heinrich Meyr (IEEE J. Sel. Areas Commun., 1990)

On the error probability of linearly modulated signals on Rayleigh frequency-flat fading channels. - Abbas Aghamohammadi; Heinrich Meyr (IEEE Trans. Commun., 1990)

High-speed parallel Viterbi decoding: algorithm and VLSI-architecture. - Gerhard P. Fettweis; Heinrich Meyr (IEEE Commun. Mag., 1991)

A new method for phase synchronization and automatic gain control of linearly modulated signals on frequency-flat fading channels. - Abbas Aghamohammadi; Heinrich Meyr; Gerd Ascheid (IEEE Trans. Commun., 1991)

Feedforward architectures for parallel Viterbi decoding. - Gerhard P. Fettweis; Heinrich Meyr (J. VLSI Signal Process., 1991)

High speed bit-level pipelined architectures for redundant CORDIC implementation. - Herbert Dawid; Heinrich Meyr (ASAP, 1992)

High level software synthesis for signal processing systems. - Sebastian Ritz; Matthias Pankert; Heinrich Meyr (ASAP, 1992)

A new mobile digital radio transceiver concept using low-complexity combined equalization/trellis decoding and a near-optimal receiver sync strategy. - Stefan A. Fechtel; Heinrich Meyr (PIMRC, 1992)

Efficient scalable architectures for Viterbi decoders. - Stefan Bitterlich; Heinrich Meyr (ASAP, 1993)

Optimum vectorization of scalable synchronous dataflow graphs. - Sebastian Ritz; Matthias Pankert; V. Zivojinovic; Heinrich Meyr (ASAP, 1993)

Partitioning and Surmounting the Software-Hardware Abstraction Gap in an ASIC Design Project. - Klaus ten Hagen; Heinrich Meyr (ICCD, 1993)

Design of optimum interpolation filters for digital demodulators. - Vojin Zivojnovic; Heinrich Meyr (ISCAS, 1993)

Matched Filter Bound for Trellis-Coded Transmission over Frequency-Selective Fading Channels with Diversity. - Stefan A. Fechtel; Heinrich Meyr (Eur. Trans. Telecommun., 1993)

High-Level Software Synthesis for the Design of Communication Systems. - Sebastian Ritz; Matthias Pankert; Vojin Zivojnovic; Heinrich Meyr (IEEE J. Sel. Areas Commun., 1993)

Dynamic data flow and control flow in high level DSP code synthesis. - Matthias Pankert; Oliver Mauss; Sebastian Ritz; Heinrich Meyr (ICASSP (2), 1994)

Retiming of DSP programs for optimum vectorization. - Vojin Zivojnovic; Sebastian Ritz; Heinrich Meyr (ICASSP (2), 1994)

Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures. - Francky Catthoor; Ed F. Deprettere; Yu Hen Hu; Jan M. Rabaey; Heinrich Meyr; Lothar Thiele (ISCAS, 1994)

High Speed FIR-Filter Architectures with Scalable Sample Rates. - Martin Vaupel; Heinrich Meyr (ISCAS, 1994)

Improved frame synchronization for spontaneous packet transmission over frequency-selective radio channels. - Stefan A. Fechtel; Heinrich Meyr (PIMRC, 1994)

Frequency synchronization algorithms for OFDM systems suitable for communication over frequency selective fading channels. - Ferdinand Classen; Heinrich Meyr (VTC, 1994)

A digital feedforward differential detection MSK receiver for packet-based mobile radio. - Uwe Lambrette; Heinrich Meyr (VTC, 1994)

Optimal parametric feedforward estimation of frequency-selective fading radio channels. - Stefan A. Fechtel; Heinrich Meyr (IEEE Trans. Commun., 1994)

On sampling rate, analog prefiltering, and sufficient statistics for digital receivers. - Heinrich Meyr; Martin Oerder; Andreas Polydoros (IEEE Trans. Commun., 1994)

High-speed VLSI architectures for soft-output viterbi decoding. - Olaf J. Joeressen; Martin Vaupel; Heinrich Meyr (J. VLSI Signal Process., 1994)

Digital Receiver Design Using VHDL Generation from Data Flow Graphs. - Peter Zepter; Thorsten Grötker; Heinrich Meyr (DAC, 1995)

ADEN: an environment for digital receiver ASIC design. - Thorsten Grötker; Peter Zepter; Heinrich Meyr (ICASSP, 1995)

DSP-based mobile and satellite receivers, from algorithm to implementation: a design course at Aachen University of Technology. - Oliver Mauss; Matthias Pankert; Ferdinand Classen; Heinrich Meyr (ICASSP, 1995)

Scheduling for optimum data memory compaction in block diagram oriented software synthesis. - Sebastian Ritz; Markus Willems; Heinrich Meyr (ICASSP, 1995)

Test Point Insertion for an Area Efficient BIST. - Claus Schotten; Heinrich Meyr (ITC, 1995)

Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding. - Herbert Dawid; Heinrich Meyr (PIMRC, 1995)

Viterbi decoding with dual timescale traceback processing. - Olaf J. Joeressen; Heinrich Meyr (PIMRC, 1995)

Advanced digital receiver principles and technologies for PCS. - Heinrich Meyr; Ravi Subramanian (IEEE Commun. Mag., 1995)

A 40 Mb/s soft-output Viterbi decoder. - Olaf J. Joeressen; Heinrich Meyr (IEEE J. Solid State Circuits, 1995)

Compiled HW/SW Co-Simulation. - Vojin Zivojnovic; Heinrich Meyr (DAC, 1996)

DSP Processor/Compiler Co-Design: A Quantitative Approach. - Vojin Zivojnovic; Stefan Pees; C. Schälger; Markus Willems; Rainer Schoenen; Heinrich Meyr (ISSS, 1996)

Codesign of a parallel architecture and an optimizing compiler backend: SIN rete processing as a case study. - Klaus ten Hagen; Dirk Steinberg; Heinrich Meyr (Des. Autom. Embed. Syst., 1996)

The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without Correcting Iterations. - Herbert Dawid; Heinrich Meyr (IEEE Trans. Computers, 1996)

A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation. - Herbert Dawid; Gerhard P. Fettweis; Heinrich Meyr (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Mapping multirate dataflow to complex RT level hardware models. - Jens Horstmannshoff; Thorsten Grötker; Heinrich Meyr (ASAP, 1997)

On core and more: a design perspective for systems-on-a-chip. - Stefan Pees; Martin Vaupel; Vojin Zivojnovic; Heinrich Meyr (ASAP, 1997)

System Level Fixed-Point Design Based on an Interpolative Approach. - Markus Willems; Volker Bürsgens; Holger Keding; Thorsten Grötker; Heinrich Meyr (DAC, 1997)

PCC: a modeling technique for mixed control/data flow systems. - Thorsten Grötker; Rainer Schoenen; Heinrich Meyr (ED&TC, 1997)

Unified specification of control and data flow. - Thorsten Grötker; Rainer Schoenen; Heinrich Meyr (ICASSP, 1997)

An upper bound of the throughput of multirate multiprocessor schedules. - Rainer Schoenen; Vojin Zivojnovic; Heinrich Meyr (ICASSP, 1997)

FRIDGE: an interactive code generation environment for HW/SW codesign. - Markus Willems; Volker Bürsgens; Thorsten Grötker; Heinrich Meyr (ICASSP, 1997)

Modulo-addressing utilization in automatic software synthesis for digital signal processors. - Markus Willems; Holger Keding; Vojin Zivojnovic; Heinrich Meyr (ICASSP, 1997)

OFDM burst frequency synchronization by single carrier training data. - Uwe Lambrette; Michael Speth; Heinrich Meyr (IEEE Commun. Lett., 1997)

Authors' reply [to "Comment on cycle slips in synchronizers subject to smooth narrow-band loop noise"]. - Marc Moeneclaey; Heinrich Meyr (IEEE Trans. Commun., 1997)

Compiled Simulation of Programmable DSP Architectures. - Vojin Zivojnovic; Steven W. K. Tjiang; Heinrich Meyr (J. VLSI Signal Process., 1997)

Digital communication receivers - synchronization, channel estimation, and signal processing. - Heinrich Meyr; Marc Moeneclaey; Stefan A. Fechtel (Wiley, 1998)

FRIDGE: A Fixed-Point Design and Simulation Environment. - Holger Keding; Markus Willems; Martin Coors; Heinrich Meyr (DATE, 1998)

Design Methodology for a DVB Satellite Receiver ASIC. - Martin Vaupel; Uwe Lambrette; Herbert Dawid; Olaf J. Joeressen; Stefan Bitterlich; Heinrich Meyr; Focko Frieling; Karsten Müller; Götz Kluge (Des. Autom. Embed. Syst., 1998)

An Aliasing-Free Receiver with Variable Sample Rate Digital Feedback M/T NDA Timing Synchronization. - Uwe Lambrette; Klaus Langhammer; Heinrich Meyr (Wirel. Pers. Commun., 1998)

LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. - Stefan Pees; Andreas Hoffmann 002; Vojin Zivojnovic; Heinrich Meyr (DAC, 1999)

Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs. - Jens Horstmannshoff; Heinrich Meyr (ISSS, 1999)

Schnelle Simulation des TI-TMS320C54x DSP. - Stefan Pees; Andreas Hoffmann 002; Andreas Ropers; Heinrich Meyr (Informationstechnik Tech. Inform., 1999)

Optimum receiver design for wireless broad-band systems using OFDM. I. - Michael Speth; Stefan A. Fechtel; Gunnar Fock; Heinrich Meyr (IEEE Trans. Commun., 1999)

Efficient building block based RTL code generation from synchronous data flow graphs. - Jens Horstmannshoff; Heinrich Meyr (DAC, 2000)

Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language. - Stefan Pees; Andreas Hoffmann 002; Heinrich Meyr (DATE, 2000)

DSP core verification using automatic test case generation. - Tilman Glökler; Stefan Bitterlich; Heinrich Meyr (ICASSP, 2000)

Iterative Multiuser Detection for Bit Interleaved Coed Modulation. - Michael Speth; Alexander Jansen; Heinrich Meyr (ICC (2), 2000)

Retargetable compiled simulation of embedded processors using a machine description language. - Stefan Pees; Andreas Hoffmann 002; Heinrich Meyr (ACM Trans. Design Autom. Electr. Syst., 2000)

Fast Bit-True Simulation. - Holger Keding; Martin Coors; Olaf Lüthje; Heinrich Meyr (DAC, 2001)

A framework for fast hardware-software co-simulation. - Andreas Hoffmann 002; Tim Kogel; Heinrich Meyr (DATE, 2001)

Generating production quality software development tools using a machine description language. - Andreas Hoffmann 002; Achim Nohl; Stefan Pees; Gunnar Braun; Heinrich Meyr (DATE, 2001)

The programmable platform: does one size fit all? - A. Lock; Raul Camposano; Heinrich Meyr (DATE, 2001)

Integer code generation for the TI TMS320C62X. - Martin Coors; Holger Keding; Olaf Lüthje; Heinrich Meyr (ICASSP, 2001)

A survey on modeling issues using the machine description language LISA. - Andreas Hoffmann 002; Achim Nohl; Gunnar Braun; Heinrich Meyr (ICASSP, 2001)

A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. - Andreas Hoffmann 002; Oliver Schliebusch; Achim Nohl; Gunnar Braun; Oliver Wahlen; Heinrich Meyr (ICCAD, 2001)

Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description. - Gunnar Braun; Andreas Hoffmann 002; Achim Nohl; Heinrich Meyr (ISSS, 2001)

Achievable rate of MIMO channels with data-aided channel estimation. - Jens Baltersee; Gunnar Fock; Heinrich Meyr (ITW, 2001)

Achievable rate of MIMO channels with data-aided channel estimation and perfect interleaving. - Jens Baltersee; Gunnar Fock; Heinrich Meyr (IEEE J. Sel. Areas Commun., 2001)

Channel tracking for RAKE receivers in closely spaced multipath environments. - Gunnar Fock; Jens Baltersee; Peter Schulz-Rittich; Heinrich Meyr (IEEE J. Sel. Areas Commun., 2001)

A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. - Andreas Hoffmann 002; Tim Kogel; Achim Nohl; Gunnar Braun; Oliver Schliebusch; Oliver Wahlen; Andreas Wieferink; Heinrich Meyr (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

An information theoretic foundation of synchronized detection. - Jens Baltersee; Gunnar Fock; Heinrich Meyr (IEEE Trans. Commun., 2001)

Optimum receiver design for OFDM-based broadband transmission .II. A case study. - Michael Speth; Stefan A. Fechtel; Gunnar Fock; Heinrich Meyr (IEEE Trans. Commun., 2001)

Architecture exploration for embedded processors with LISA. - Andreas Hoffmann 002; Heinrich Meyr; Rainer Leupers (Kluwer, 2002)

Low complexity high resolution subspace-based delay estimation for DS-CDMA. - Gunnar Fock; Peter Schulz-Rittich; Andreas Schenke; Heinrich Meyr (ICC, 2002)

Designing SoC's. - Tobias Noll; Heinrich Meyr (ISLPED, 2002)

Application specific compiler/architecture codesign: a case study. - Oliver Wahlen; Tilman Glökler; Achim Nohl; Andreas Hoffmann 002; Rainer Leupers; Heinrich Meyr (LCTES-SCOPES, 2002)

Architecture Implementation Using the Machine Description Language LISA. - Oliver Schliebusch; Andreas Hoffmann 002; Achim Nohl; Gunnar Braun; Heinrich Meyr (ASP-DAC/VLSI Design, 2002)

Design and DSP Implementation of Fixed-Point Systems. - Martin Coors; Holger Keding; Olaf Lüthje; Heinrich Meyr (EURASIP J. Adv. Signal Process., 2002)

A modular simulation framework for architectural exploration of on-chip interconnection networks. - Tim Kogel; Malte Doerper; Andreas Wieferink; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Serge Goossens (CODES+ISSS, 2003)

Instruction encoding synthesis for architecture exploration using hierarchical processor models. - Achim Nohl; Volker Greive; Gunnar Braun; Andreas Hoffmann 002; Rainer Leupers; Oliver Schliebusch; Heinrich Meyr (DAC, 2003)

Processor/Memory Co-Exploration on Multiple Abstraction Levels. - Gunnar Braun; Andreas Wieferink; Oliver Schliebusch; Rainer Leupers; Heinrich Meyr; Achim Nohl (DATE, 2003)

Initial synchronization of W-CDMA systems using a power-scaled detector with antenna diversity in frequency-selective Rayleigh fading channels. - Lars Schmitt; Volker Simon; Thomas Grundler; Christoph Schreyoegg; Heinrich Meyr (GLOBECOM, 2003)

The effect of imperfect SNR knowledge on multiantenna multiuser systems with channel aware scheduling. - Peter Schulz-Rittich; Andreas Senst; Thomas Bilke; Heinrich Meyr (GLOBECOM, 2003)

Synchronization requirements for COFDM systems with transmit diversity. - Michael Speth; Heinrich Meyr (GLOBECOM, 2003)

Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. - Oliver Wahlen; Manuel Hohenauer; Gunnar Braun; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Xiaoning Nie (SCOPES, 2003)

Instruction Scheduler Generation for Retargetable Compilation. - Oliver Wahlen; Manuel Hohenauer; Rainer Leupers; Heinrich Meyr (IEEE Des. Test Comput., 2003)

Methodical Low-Power ASIP Design Space Exploration. - Tilman Glökler; Andreas Hoffmann 002; Heinrich Meyr (J. VLSI Signal Process., 2003)

A novel approach for flexible and consistent ADL-driven ASIP design. - Gunnar Braun; Achim Nohl; Weihua Sheng; Jianjiang Ceng; Manuel Hohenauer; Hanno Scharwächter; Rainer Leupers; Heinrich Meyr (DAC, 2004)

Heterogeneous MP-SoC: the solution to energy-efficient signal processing. - Tim Kogel; Heinrich Meyr (DAC, 2004)

A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. - Manuel Hohenauer; Hanno Scharwächter; Kingshuk Karuri; Oliver Wahlen; Tim Kogel; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Gunnar Braun; Hans van Someren 001 (DATE, 2004)

RTL Processor Synthesis for Architecture Exploration and Implementation. - Oliver Schliebusch; Anupam Chattopadhyay; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Mario Steinert; Gunnar Braun; Achim Nohl (DATE, 2004)

A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. - Andreas Wieferink; Tim Kogel; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Gunnar Braun; Achim Nohl (DATE, 2004)

Performance of initial synchronization schemes for WCDMA systems with spatio-temporal correlations. - Lars Schmitt; Thomas Grundler; Christoph Schreyoegg; Gerd Ascheid; Heinrich Meyr (ICC, 2004)

Random beamforming in correlated MISO channels for multiuser systems. - Andreas Senst; Peter Schulz-Rittich; Ulrich Krause; Gerd Ascheid; Heinrich Meyr (ICC, 2004)

Application specific instruction-set processors (ASIP's) for wireless communications: design, cost, and energy efficiency vs. flexibility. - Heinrich Meyr (SoC, 2004)

Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. - Tim Kogel; Malte Doerper; Torsten Kempf; Andreas Wieferink; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (SAMOS, 2004)

Early ISS Integration into Network-on-Chip Designs. - Andreas Wieferink; Malte Doerper; Tim Kogel; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (SAMOS, 2004)

Stochastic modeling of the convergence behavior of concatenated codes. - Rudolf Mathar; Heinrich Meyr (VTC Fall (2), 2004)

A universal technique for fast and flexible instruction-set architecture simulation. - Gunnar Braun; Achim Nohl; Andreas Hoffmann 002; Oliver Schliebusch; Rainer Leupers; Heinrich Meyr (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. - Mohammad Mostafizur Rahman Mozumdar; Kingshuk Karuri; Anupam Chattopadhyay; Stefan Kraemer; Hanno Scharwächter; Heinrich Meyr; Gerd Ascheid; Rainer Leupers (ASAP, 2005)

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. - Oliver Schliebusch; Anupam Chattopadhyay; David Kammler; Gerd Ascheid; Rainer Leupers; Heinrich Meyr; Tim Kogel (ASP-DAC, 2005)

Retargetable generation of TLM bus interfaces for MP-SoC platforms. - Andreas Wieferink; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Tom Michiels; Achim Nohl; Tim Kogel (CODES+ISSS, 2005)

Fine-grained application source code profiling for ASIP design. - Kingshuk Karuri; Mohammad Abdullah Al Faruque; Stefan Kraemer; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (DAC, 2005)

C Compiler Retargeting Based on Instruction Semantics Models. - Jianjiang Ceng; Manuel Hohenauer; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Gunnar Braun (DATE, 2005)

A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. - Torsten Kempf; Malte Doerper; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Tim Kogel; Bart Vanthournout (DATE, 2005)

Improving MIMO phase noise estimation by exploiting spatial correlations. - Niels Hadaschik; Meik Dörpinghaus; Andreas Senst; Ole Harmjanz; Uwe Käufer; Gerd Ascheid; Heinrich Meyr (ICASSP (3), 2005)

Optimization Techniques for ADL-Driven RTL Processor Synthesis. - Oliver Schliebusch; Anupam Chattopadhyay; Ernst Martin Witte; David Kammler; Gerd Ascheid; Rainer Leupers; Heinrich Meyr (IEEE International Workshop on Rapid System Prototyping, 2005)

Integrated system-level modeling of network-on-chip enabled multi-processor platforms. - Tim Kogel; Rainer Leupers; Heinrich Meyr (Kluwer, 2006)

Retargetable code optimization with SIMD instructions. - Manuel Hohenauer; Christoph Schumacher; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Hans van Someren 001 (CODES+ISSS, 2006)

Automatic ADL-based operand isolation for embedded processors. - Anupam Chattopadhyay; Benedikt Geukes; David Kammler; Ernst Martin Witte; Oliver Schliebusch; Harold Ishebabi; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (DATE, 2006)

ASIP design and synthesis for non linear filtering in image processing. - Luca Fanucci; Michele Cassiano; Sergio Saponara; David Kammler; Ernst Martin Witte; Oliver Schliebusch; Gerd Ascheid; Rainer Leupers; Heinrich Meyr (DATE Designers' Forum, 2006)

Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. - Kingshuk Karuri; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Monu Kedia (DATE Designers' Forum, 2006)

A SW performance estimation framework for early system-level-design using fine-grained instrumentation. - Torsten Kempf; Kingshuk Karuri; Stefan Wallentowitz; Gerd Ascheid; Rainer Leupers; Heinrich Meyr (DATE, 2006)

An interprocedural code optimization technique for network processors using hardware multi-threading support. - Hanno Scharwächter; Manuel Hohenauer; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (DATE, 2006)

Memory Access Micro-Profiling for ASIP Design. - Kingshuk Karuri; Christian Huben; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (DELTA, 2006)

Design of Application Specific Processors for the Cached FFT Algorithm. - Oguzhan Atak; Abdullah Atalar; Erdal Arikan; Harold Ishebabi; David Kammler; Gerd Ascheid; Heinrich Meyr; Mario Nicola; Guido Masera (ICASSP (3), 2006)

Enhanced Predictive Up/Down Power Control for CDMA Systems. - Meik Dörpinghaus; Lars Schmitt; Ingo Viering; Axel Klein; Joachim Schmid 001; Gerd Ascheid; Heinrich Meyr (ICC, 2006)

An efficient parallelization technique for high throughput FFT-ASIPs. - Harold Ishebabi; Gerd Ascheid; Heinrich Meyr; Oguzhan Atak; Abdullah Atalar; Erdal Arikan (ISCAS, 2006)

Flexibility and low power: a contradiction in terms? - Peter Wintermayr; Reiner W. Hartenstein; Heinrich Meyr; Steve Leibson (ISLPED, 2006)

Achievable Data Rate of Wideband OFDM With Data-Aided Channel Estimation. - Niels Hadaschik; Gerd Ascheid; Heinrich Meyr (PIMRC, 2006)

Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. - Jianjiang Ceng; Weihua Sheng; Manuel Hohenauer; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Gunnar Braun (J. VLSI Signal Process., 2006)

Optimized ASIP synthesis from architecture description language models. - Oliver Schliebusch; Heinrich Meyr; Rainer Leupers (Kluwer, 2007)

A fast and generic hybrid simulation approach using C virtual machine. - Lei Gao; Stefan Kraemer; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (CASES, 2007)

HySim: a fast simulation framework for embedded software development. - Stefan Kraemer; Lei Gao; Jan Weinstock; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (CODES+ISSS, 2007)

A code-generator generator for multi-output instructions. - Hanno Scharwächter; Jonghee M. Youn; Rainer Leupers; Yunheung Paek; Gerd Ascheid; Heinrich Meyr (CODES+ISSS, 2007)

Design space exploration of partially re-configurable embedded processors. - Anupam Chattopadhyay; W. Ahmed; Kingshuk Karuri; David Kammler; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (DATE, 2007)

Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. - Stefan Kraemer; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (DATE, 2007)

Joint Reduction of Peak-to-Average Power Ratio and Out-of-Band Power in OFDM Systems. - Martin Senst; Markus Jordan; Meik Dorpinghaus; Michael Farber; Gerd Ascheid; Heinrich Meyr (GLOBECOM, 2007)

Increasing data-bandwidth to instruction-set extensions through register clustering. - Kingshuk Karuri; Anupam Chattopadhyay; Manuel Hohenauer; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (ICCAD, 2007)

Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. - Anupam Chattopadhyay; Zoltan Endre Rakosi; Kingshuk Karuri; David Kammler; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (IEEE International Workshop on Rapid System Prototyping, 2007)

On the Influence of Pilot Symbol and Data Symbol Positioning on Turbo Synchronization. - Susanne Godtmann; André Pollok; Niels Hadaschik; Gerd Ascheid; Heinrich Meyr (VTC Spring, 2007)

Performance Evaluation of Opportunistic Beamforming with SINR Prediction for HSDPA. - Markus Jordan; Gerd Ascheid; Heinrich Meyr (VTC Spring, 2007)

Prediction of Downlink SNR for Opportunistic Beamforming. - Markus Jordan; Lars Schmitt; Gerd Ascheid; Heinrich Meyr (WCNC, 2007)

ASIP architecture exploration for efficient IPSec encryption: A case study. - Hanno Scharwächter; David Kammler; Andreas Wieferink; Manuel Hohenauer; Kingshuk Karuri; Jianjiang Ceng; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (ACM Trans. Embed. Comput. Syst., 2007)

MAPS: an integrated framework for MPSoC application parallelization. - Jianjiang Ceng; Jerónimo Castrillón; Weihua Sheng; Hanno Scharwächter; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Tsuyoshi Isshiki; Hiroaki Kunieda (DAC, 2008)

Multiprocessor performance estimation using hybrid simulation. - Lei Gao; Kingshuk Karuri; Stefan Kraemer; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (DAC, 2008)

High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. - Anupam Chattopadhyay; Xiaolin Chen; Harold Ishebabi; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (DATE, 2008)

Retargetable Code Optimization for Predicated Execution. - Manuel Hohenauer; Felix Engel 001; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Gerrit Bette; Balpreet Singh (DATE, 2008)

Asymptotic BER Analysis for MIMO-BICM with Zero-Forcing Detectors Assuming Imperfect CSI. - I-Wei Lai; Susanne Godtmann; Tzi-Dar Chiueh; Gerd Ascheid; Heinrich Meyr (ICC, 2008)

Optimal PSK signaling over stationary Rayleigh fading channels. - Meik Dörpinghaus; Gerd Ascheid; Heinrich Meyr; Rudolf Mathar (ISIT, 2008)

Long-Term Beamforming in Single Frequency Networks using Semidefinite Relaxation. - Markus Jordan; Martin Senst; Gerd Ascheid; Heinrich Meyr (VTC Spring, 2008)

Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. - Tim Kogel; Malte Doerper; Torsten Kempf; Andreas Wieferink; Rainer Leupers; Heinrich Meyr (Int. J. Embed. Syst., 2008)

SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends. - Andreas Wieferink; Tim Kogel; Olaf Zerres; Rainer Leupers; Heinrich Meyr (Int. J. Embed. Syst., 2008)

Power-efficient Instruction Encoding Optimization for Various Architecture Classes. - Diandian Zhang; Anupam Chattopadhyay; David Kammler; Ernst Martin Witte; Gerd Ascheid; Rainer Leupers; Heinrich Meyr (J. Comput., 2008)

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. - Anupam Chattopadhyay; Harold Ishebabi; Xiaolin Chen; Zoltan Endre Rakosi; Kingshuk Karuri; David Kammler; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (ACM Trans. Embed. Comput. Syst., 2008)

A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors. - Kingshuk Karuri; Anupam Chattopadhyay; Xiaolin Chen; David Kammler; Ling Hao; Rainer Leupers; Heinrich Meyr; Gerd Ascheid (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Tight Approximation of the Bit Error Rate for BICM(-ID) Assuming Imperfect CSI. - Susanne Godtmann; I-Wei Lai; Gerd Ascheid; Tzi-Dar Chiueh; Heinrich Meyr (IEEE Trans. Wirel. Commun., 2008)

A high-level virtual platform for early MPSoC software development. - Jianjiang Ceng; Weihua Sheng; Jerónimo Castrillón; Anastasia Stulova; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (CODES+ISSS, 2009)

TotalProf: a fast and accurate retargetable source code profiler. - Lei Gao; Jia Huang; Jianjiang Ceng; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (CODES+ISSS, 2009)

Searching in the Delta Lattice: An Efficient MIMO Detection for Iterative Receivers. - I-Wei Lai; Chun-Hao Liao; Ernst Martin Witte; David Kammler; Filippo Borlenghi; Konstantinos Nikitopoulos; Venkatesh Ramakrishnan; Dan Zhang 003; Tzi-Dar Chiueh; Gerd Ascheid; Heinrich Meyr (GLOBECOM, 2009)

Automatic generation of memory interfaces. - David Kammler; Bastian Bauwens; Ernst Martin Witte; Gerd Ascheid; Rainer Leupers; Heinrich Meyr; Anupam Chattopadhyay (SoC, 2009)

Combining orthogonalized partial metrics: Efficient enumeration for soft-input sphere decoder. - Chun-Hao Liao; I-Wei Lai; Konstantinos Nikitopoulos; Filippo Borlenghi; David Kammler; Ernst Martin Witte; Dan Zhang 003; Tzi-Dar Chiueh; Gerd Ascheid; Heinrich Meyr (PIMRC, 2009)

Efficient implementations from libraries: Analyzing the influence of configuration parameters on key performance properties. - Venkatesh Ramakrishnan; Joschka zur Jacobsmuehlen; I-Wei Lai; Torsten Kempf; Marc Adrat; Gerd Ascheid; Markus Antweiler; Heinrich Meyr (PIMRC, 2009)

A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). - Kingshuk Karuri; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (SAMOS, 2009)

A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations. - David Kammler; Junqing Guan; Gerd Ascheid; Rainer Leupers; Heinrich Meyr (SSIRI, 2009)

A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. - Torsten Kempf; Stefan Wallentowitz; Gerd Ascheid; Rainer Leupers; Heinrich Meyr (VLSI Design, 2009)

Low-Complexity Channel-Adaptive MIMO Detection with Just-Acceptable Error Rate. - I-Wei Lai; Gerd Ascheid; Heinrich Meyr; Tzi-Dar Chiueh (VTC Spring, 2009)

Efficient And Portable SDR Waveform Development: The Nucleus Concept - Venkatesh Ramakrishnan; Ernst Martin Witte; Torsten Kempf; David Kammler; Gerd Ascheid; Heinrich Meyr; Marc Adrat; Markus Antweiler (CoRR, 2009)

A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding - Ernst Martin Witte; Filippo Borlenghi; Gerd Ascheid; Rainer Leupers; Heinrich Meyr (CoRR, 2009)

Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. - David Kammler; Diandian Zhang; Peter Schwabe; Hanno Scharwächter; Markus Langenberg; Dominik Auras; Gerd Ascheid; Rainer Leupers; Rudolf Mathar; Heinrich Meyr (IACR Cryptol. ePrint Arch., 2009)

Integrated verification approach during ADL-driven processor design. - Anupam Chattopadhyay; Arnab Sinha; Diandian Zhang; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (Microelectron. J., 2009)

A SIMD optimization framework for retargetable compilers. - Manuel Hohenauer; Felix Engel 001; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (ACM Trans. Archit. Code Optim., 2009)

Iterative channel estimation control for MIMO-OFDM Systems. - Dan Zhang 003; Konstantinos Nikitopoulos; I-Wei Lai; Gerd Ascheid; Heinrich Meyr (CISS, 2010)

Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. - Jerónimo Castrillón; Ricardo Velasquez; Anastasia Stulova; Weihua Sheng; Jianjiang Ceng; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (DATE, 2010)

The achievable rate of stationary rayleigh flat-fading channels with IID input symbols. - Meik Dorpinghaus; Heinrich Meyr; Gerd Ascheid (ISITA, 2010)

BER analysis for MIMO BICM-ID assuming finite precision of extrinsic LLR. - Chien-Yi Wang; I-Wei Lai; Tzi-Dar Chiueh; Gerd Ascheid; Heinrich Meyr (ISITA, 2010)

2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures. - Cristina Silvano; William Fornaciari; Stefano Crespi-Reghizzi; Giovanni Agosta; Gianluca Palermo; Vittorio Zaccaria; Patrick Bellasi; Fabrizio Castro; Simone Corbetta; Andrea Di Biagio; Ettore Speziale; Michele Tartara; et al. (ISVLSI (Selected papers), 2010)

2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures. - Cristina Silvano; William Fornaciari; Stefano Crespi-Reghizzi; Giovanni Agosta; Gianluca Palermo; Vittorio Zaccaria; Patrick Bellasi; Fabrizio Castro; Simone Corbetta; Andrea Di Biagio; Ettore Speziale; Michele Tartara; et al. (ISVLSI, 2010)

Automatic Generation of Memory Interfaces for ASIPs. - David Kammler; Ernst Martin Witte; Anupam Chattopadhyay; Bastian Bauwens; Gerd Ascheid; Rainer Leupers; Heinrich Meyr (Int. J. Embed. Real Time Commun. Syst., 2010)

Analytical and Simulation-based Design Space Exploration of Software Defined Radios. - Torsten Kempf; Stefan Wallentowitz; Gerd Ascheid; Rainer Leupers; Heinrich Meyr (Int. J. Parallel Program., 2010)

A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding. - Ernst Martin Witte; Filippo Borlenghi; Gerd Ascheid; Rainer Leupers; Heinrich Meyr (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A Systematic Framework for Iterative Maximum Likelihood Receiver Design. - Lars Schmitt; Heinrich Meyr (IEEE Trans. Commun., 2010)

Systematic Design of Iterative ML Receivers for Flat Fading Channels. - Lars Schmitt; Heinrich Meyr; Dan Zhang 003 (IEEE Trans. Commun., 2010)

A 772Mbit/s 8.81bit/nJ 90nm CMOS soft-input soft-output sphere decoder. - Filippo Borlenghi; Ernst Martin Witte; Gerd Ascheid; Heinrich Meyr; Andreas Peter Burg (A-SSCC, 2011)

Asymptotic BER Analysis for MIMO-BICM with MMSE Detection and Channel Estimation. - I-Wei Lai; Gerd Ascheid; Heinrich Meyr; Tzi-Dar Chiueh (ICC, 2011)

Achievable rate with receivers using iterative channel estimation in stationary fading channels. - Meik Dorpinghaus; Adrian Ispas; Heinrich Meyr (ISWCS, 2011)

On the Achievable Rate of Stationary Rayleigh Flat-Fading Channels with Gaussian Inputs - Meik Dörpinghaus; Heinrich Meyr (CoRR, 2011)

A retargetable framework for compiler/architecture co-development. - Hanno Scharwächter; David Kammler; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (Des. Autom. Embed. Syst., 2011)

On Complexity, Energy- and Implementation-Efficiency of Channel Decoders. - Frank Kienle; Norbert Wehn; Heinrich Meyr (IEEE Trans. Commun., 2011)

Efficient Channel-Adaptive MIMO Detection Using Just-Acceptable Error Rate. - I-Wei Lai; Gerd Ascheid; Heinrich Meyr; Tzi-Dar Chiueh (IEEE Trans. Wirel. Commun., 2011)

A 2.78 mm2 65 nm CMOS gigabit MIMO iterative detection and decoding receiver. - Filippo Borlenghi; Ernst Martin Witte; Gerd Ascheid; Heinrich Meyr; Andreas Burg 001 (ESSCIRC, 2012)

Searching for optimal scheduling of MIMO doubly iterative receivers: An ant colony optimization-based method. - Dan Zhang 003; Gaojian Wang; Gerd Ascheid; Heinrich Meyr (GLOBECOM, 2012)

Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach. - Cristina Silvano; William Fornaciari; Stefano Crespi-Reghizzi; Giovanni Agosta; Gianluca Palermo; Vittorio Zaccaria; Patrick Bellasi; Fabrizio Castro; Simone Corbetta; Ettore Speziale; Diego Melpignano; J. M. Zins; et al. (INA-OCMC@HiPEAC, 2012)

An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems. - Filippo Borlenghi; Dominik Auras; Ernst Martin Witte; Torsten Kempf; Gerd Ascheid; Rainer Leupers; Heinrich Meyr (ICSAMOS, 2012)

Asymptotic Coded BER Analysis for MIMO BICM-ID with Quantized Extrinsic LLR. - I-Wei Lai; Chien-Yi Wang; Tzi-Dar Chiueh; Gerd Ascheid; Heinrich Meyr (IEEE Trans. Commun., 2012)

On the Gain of Joint Processing of Pilot and Data Symbols in Stationary Rayleigh Fading Channels. - Meik Dorpinghaus; Adrian Ispas; Heinrich Meyr (IEEE Trans. Inf. Theory, 2012)

On the Achievable Rate of Stationary Rayleigh Flat-Fading Channels With Gaussian Inputs. - Meik Dorpinghaus; Heinrich Meyr; Rudolf Mathar (IEEE Trans. Inf. Theory, 2013)

Oversampling Increases the Pre-Log of Noncoherent Fading Channels. - Meik Dörpinghaus; Günther Koliander; Giuseppe Durisi; Erwin Riegler; Heinrich Meyr (CoRR, 2014)

Oversampling Increases the Pre-Log of Noncoherent Rayleigh Fading Channels. - Meik Dörpinghaus; Günther Koliander; Giuseppe Durisi; Erwin Riegler; Heinrich Meyr (IEEE Trans. Inf. Theory, 2014)

Channel-aware local search (CA-LS) for iterative MIMO detection. - I-Wei Lai; Chia-Han Lee; Gerd Ascheid; Heinrich Meyr; Tzi-Dar Chiueh (PIMRC, 2015)

An information theoretic analysis of sequential decision-making. - Meik Dorpinghaus; Édgar Roldán; Izaak Neri; Heinrich Meyr; Frank Jülicher (ISIT, 2017)

On the Performance Gap Between ML and Iterative Decoding of Finite-Length Turbo-Coded BICM in MIMO Systems. - Dan Zhang 003; Heinrich Meyr (IEEE Trans. Commun., 2017)

Testing Optimality of Sequential Decision-Making. - Meik Dörpinghaus; Izaak Neri; Édgar Roldán; Heinrich Meyr; Frank Jülicher (CoRR, 2018)

Observability Analysis of Flight State Estimation for UAVs and Experimental Validation. - Peng Huang; Heinrich Meyr; Meik Dörpinghaus; Gerhard P. Fettweis (ICRA, 2020)