CMOS fault modeling, test generation and design for testability. - C. Matthäus; B. Krüger-Sprengel; C. Glowacz; Uwe Hübner; Heinrich Theodor Vierhaus (Microprocess. Microprogramming, 1988)

Testability of non-trivial CMOS faults under realistic conditions. - Heinrich Theodor Vierhaus (Microprocessing and Microprogramming, 1989)

CMOS layout generation for improved testability. - Olaf Stern; Heinrich Theodor Vierhaus (Microprocessing and Microprogramming, 1990)

Mixed level test generation for high fault coverage. - Uwe Hübner; H. Hinsen; M. Hofebauer; Heinrich Theodor Vierhaus (Microprocessing and Microprogramming, 1991)

MILEF: an efficient approach to mixed level automatic test pattern generation. - Uwe Gläser; Heinrich Theodor Vierhaus (EURO-DAC, 1992)

Efficient partitioning and analysis of digital CMOS-circuits. - Uwe Hübner; Heinrich Theodor Vierhaus (ICCAD, 1992)

Library Mapping of CMOS-Switch-Level-Circuits by Extraction of Isomorphic Subgraphs. - Ursula Westerholz; Heinrich Theodor Vierhaus (ICCD, 1992)

Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects. - Uwe Gläser; Uwe Hübner; Heinrich Theodor Vierhaus (ITC, 1992)

CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents. - Uwe Hübner; Wolfgang Meyer 002; Heinrich Theodor Vierhaus (Microprocess. Microprogramming, 1992)

CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects. - Heinrich Theodor Vierhaus; Wolfgang Meyer 002; Uwe Gläser (ITC, 1993)

Fault behavior and testability of asynchronous CMOS circuits. - Heinrich Theodor Vierhaus; Wolfgang Meyer 002; Uwe Gläser; Raul Camposano (Microprocess. Microprogramming, 1993)

Local microcode generation in system design. - Michel Langevin; Eduard Cerny; Jörg Wilberg; Heinrich Theodor Vierhaus (Code Generation for Embedded Processors, 1994)

Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation. - Uwe Gläser; Heinrich Theodor Vierhaus; M. Kley; A. Wiederhold (ICCAD, 1994)

Testability Analysis for Test Generation in Synchronous Sequential Circuits. - R. Wolber; Uwe Gläser; Heinrich Theodor Vierhaus (ICCD, 1994)

Gate delay fault test generation for non-scan circuits. - G. Van Brakel; Uwe Gläser; Hans G. Kerkhoff; Heinrich Theodor Vierhaus (ED&TC, 1995)

FOGBUSTER: an efficient algorithm for sequential test generation. - Uwe Gläser; Heinrich Theodor Vierhaus (EURO-DAC, 1995)

Improving topological ATPG with symbolic techniques. - Fulvio Corno; Paolo Prinetto; Matteo Sonza Reorda; Uwe Gläser; Heinrich Theodor Vierhaus (VTS, 1995)

A Design Exploration Environment. - Jörg Wilberg; A. Kuth; Raul Camposano; Wolfgang Rosenstiel; Heinrich Theodor Vierhaus (Great Lakes Symposium on VLSI, 1996)

Automatic Test Pattern Generation with Optimal Load Balancing. - H.-Ch. Dahmen; Uwe Gläser; Heinrich Theodor Vierhaus (PVM, 1996)

Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm. - Uwe Gläser; Heinrich Theodor Vierhaus (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation. - H.-Ch. Dahmen; Uwe Gläser; Heinrich Theodor Vierhaus (Great Lakes Symposium on VLSI, 1997)

A Parallel Approach Solving the Test Generation Problem for Synchronous Sequential Circuits. - H.-Ch. Dahmen; Uwe Gläser; Heinrich Theodor Vierhaus (PARCO, 1997)

Partitioning and analysis of static digital CMOS circuits. - Uwe Hübner; Heinrich Theodor Vierhaus; Raul Camposano (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Generating reliable embedded processors. - Matthias Pflanz; Heinrich Theodor Vierhaus (IEEE Micro, 1998)

An efficient on-line-test and back-up scheme for embedded processors. - Matthias Pflanz; Heinrich Theodor Vierhaus; F. Pompsch (ITC, 1999)

SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. - Fulvio Corno; Uwe Gläser; Paolo Prinetto; Matteo Sonza Reorda; Heinrich Theodor Vierhaus; Massimo Violante (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A new method for on-line state machine observation for embedded microprocessors. - Matthias Pflanz; Christian Galke; Heinrich Theodor Vierhaus (HLDVT, 2000)

A register-transfer-level fault simulator for permanent and transient faults in embedded processors. - C. Rousselle; Matthias Pflanz; A. Behling; T. Mohaupt; Heinrich Theodor Vierhaus (DATE, 2001)

On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity. - Matthias Pflanz; Karsten Walther; Heinrich Theodor Vierhaus (IOLTW, 2001)

Online Check and Recovery Techniques for Dependable Embedded Processors. - Matthias Pflanz; Heinrich Theodor Vierhaus (IEEE Micro, 2001)

A Test Processor Concept for Systems-on-a-Chip. - Christian Galke; Matthias Pflanz; Heinrich Theodor Vierhaus (ICCD, 2002)

On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures. - Christian Galke; Matthias Pflanz; Heinrich Theodor Vierhaus (IOLTW, 2002)

On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check. - Matthias Pflanz; Karsten Walther; Christian Galke; Heinrich Theodor Vierhaus (IOLTW, 2002)

Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip. - Christian Galke; Marcus Grabow; Heinrich Theodor Vierhaus (IOLTS, 2003)

Control Signal Protection For High Performance Processors. - Matthias Pflanz; Heinrich Theodor Vierhaus (IOLTS, 2003)

On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check. - Matthias Pflanz; Karsten Walther; Christian Galke; Heinrich Theodor Vierhaus (J. Electron. Test., 2003)

A Hierarchical Self Test Scheme for SoCs. - Claudia Kretzschmar; Christian Galke; Heinrich Theodor Vierhaus (IOLTS, 2004)

FIT - A Parallel Hierarchical Fault Simulation Environment. - Silvio Misera; Heinrich Theodor Vierhaus (PARELEC, 2004)

Power-/Timing - Optimierung für Zellen-basierte Digitalschaltungen in Submikron-Technologien. - Heinrich Theodor Vierhaus; Helmut Rossmann (GI Jahrestagung (1), 2005)

A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features. - René Kothe; Christian Galke; Heinrich Theodor Vierhaus (IOLTS, 2005)

Synchronization Fault Cryptanalysis for Breaking A5/1. - Marcin Gomulkiewicz; Miroslaw Kutylowski; Heinrich Theodor Vierhaus; Pawel Wlaz (WEA, 2005)

Logic Self Repair. - Christian Galke; René Kothe; Heinrich Theodor Vierhaus (ARCS Workshops, 2006)

Evaluating coverage of error detection logic for soft errors using formal methods. - Udo Krautz; Matthias Pflanz; Christian Jacobi 002; Hans-Werner Tast; Kai Weber 001; Heinrich Theodor Vierhaus (DATE, 2006)

Hardware/Software Based Hierarchical Self Test for SoCs. - René Kothe; Christian Galke; Sabine Schultke; Henry Fröschke; Steffen Gaede; Heinrich Theodor Vierhaus (DDECS, 2006)

Embedded Self Repair by Transistor and Gate Level Reconfiguration. - René Kothe; Heinrich Theodor Vierhaus; Torsten Coym; Wolfgang Vermeiren; Bernd Straube (DDECS, 2006)

Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes. - Christian Galke; U. Gätzschmann; Heinrich Theodor Vierhaus (DSD, 2006)

A Mixed Language Fault Simulation of VHDL and SystemC. - Silvio Misera; Heinrich Theodor Vierhaus; Lars Breitenfeld; André Sieber (DSD, 2006)

Embedded Scan Test with Diagnostic Features for Self-Testing SoCs. - Christian Galke; René Kothe; Sabine Schultke; K. Winkler; Jeanette Honko; Heinrich Theodor Vierhaus (IOLTS, 2006)

Built-in Self Repair by Reconfiguration of FPGAs. - S. Habermann; René Kothe; Heinrich Theodor Vierhaus (IOLTS, 2006)

Timing-/Power-getriebener Layout-Entwurf für Zellen-basierte Digitalschaltungen. - Axel Vick; Helmut Rossmann; Heinrich Theodor Vierhaus (MBMV, 2006)

Flip-Flops and Scan-Path Elements for Nanoelectronics. - René Kothe; Heinrich Theodor Vierhaus (DDECS, 2007)

Fault Injection Techniques and their Accelerated Simulation in SystemC. - Silvio Misera; Heinrich Theodor Vierhaus; André Sieber (DSD, 2007)

Timing- / Power-Optimization for Digital Logic Based on Standard Cells. - Heinrich Theodor Vierhaus; Helmut Rossmann; Silvio Misera (DSD, 2007)

A Configurable Modular Test Processor and Scan Controller Architecture. - R. Frost; D. Rudolph; Christian Galke; René Kothe; Heinrich Theodor Vierhaus (IOLTS, 2007)

Embedded Diagnostic Logic Test Exploiting Regularity. - Heinrich Theodor Vierhaus; René Kothe (DSD, 2008)

Basic Architecture for Logic Self Repair. - Tobias Koal; Heinrich Theodor Vierhaus (IOLTS, 2008)

A Scan Controller Concept for Low Power Scan Tests. - René Kothe; Heinrich Theodor Vierhaus (J. Low Power Electron., 2008)

Simulated fault injections and their acceleration in SystemC. - Silvio Misera; Heinrich Theodor Vierhaus; André Sieber (Microprocess. Microsystems, 2008)

A scheme of logic self repair including local interconnects. - Tobias Koal; Daniel Scheit; Heinrich Theodor Vierhaus (DDECS, 2009)

Reliability Estimation Process. - Tobias Koal; Daniel Scheit; Heinrich Theodor Vierhaus (DSD, 2009)

A Concept for Logic Self Repair. - Tobias Koal; Heinrich Theodor Vierhaus; Daniel Scheit (DSD, 2009)

A software-based self-test and hardware reconfiguration solution for VLIW processors. - Tobias Koal; Heinrich Theodor Vierhaus (DDECS, 2010)

Combining de-stressing and self repair for long-term dependable systems. - Tobias Koal; Heinrich Theodor Vierhaus (DDECS, 2010)

Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures. - René Kothe; Heinrich Theodor Vierhaus (DSD, 2010)

Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair. - Tobias Koal; Heinrich Theodor Vierhaus (DDECS, 2011)

A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors. - Markus Ulbricht 002; Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus (DDECS, 2011)

On the Feasibility of Built-In Self Repair for Logic Circuits. - Tobias Koal; Daniel Scheit; Mario Schölzel; Heinrich Theodor Vierhaus (DFT, 2011)

Hierarchical Self-repair in Heterogeneous Multi-core Systems by Means of a Software-based Reconfiguration. - Sebastian Müller 005; Mario Schölzel; Heinrich Theodor Vierhaus (ARCS Workshops, 2012)

Combining on-line fault detection and logic self repair. - Tobias Koal; Markus Ulbricht 002; Heinrich Theodor Vierhaus (DDECS, 2012)

An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores. - Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus (DDECS, 2012)

Scan Based Tests via Standard Interfaces. - Christian Gleichner; Heinrich Theodor Vierhaus; Piet Engelke (DSD, 2012)

Activity Migration in M-of-N-Systems by Means of Load-Balancing. - Markus Ulbricht 002; Heinrich Theodor Vierhaus; Tobias Koal (DSD, 2012)

On the feasibility of combining on-line-test and self repair for logic circuits. - Tobias Koal; Markus Ulbricht 002; Piet Engelke; Heinrich Theodor Vierhaus (DDECS, 2013)

On performance estimation of a scalable VLIW soft-core in XILINX FPGAs. - Petr Pfeifer; Zdenek Plíva; Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus (DDECS, 2013)

Virtual TMR Schemes Combining Fault Tolerance and Self Repair. - Tobias Koal; Markus Ulbricht 002; Heinrich Theodor Vierhaus (DSD, 2013)

Towards an automatic generation of diagnostic in-field SBST for processor components. - Mario Schölzel; Tobias Koal; Stephanie Roder; Heinrich Theodor Vierhaus (LATW, 2013)

Ein konfigurierbarer Zwischencodesimulator zum compilerzentrierten Mikroprozessorentwurf. - Roberto Urban; Mario Schölzel; Heinrich Theodor Vierhaus (MBMV, 2013)

Towards a Graceful Degradable Multicore-System by Hierarchical Handling of Hard Errors. - Sebastian Müller 005; Mario Schölzel; Heinrich Theodor Vierhaus (PDP, 2013)

Combining fault tolerance and self repair at minimum cost in power and hardware. - Tobias Koal; Mario Schölzel; Heinrich Theodor Vierhaus (DDECS, 2014)

Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults. - Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus (DFT, 2014)

Reconfigurable high performance architectures: How much are they ready for safety-critical applications? - Davide Sabena; Luca Sterpone; Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus; S. Wong; Robért Glein; Florian Rittner; C. Stender; Mario Porrmann; Jens Hagemeyer (ETS, 2014)

Systematic generation of diagnostic software-based self-test routines for processor components. - Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus (ETS, 2014)

Advanced technical education in the age of cyber physical systems. - Heinrich Theodor Vierhaus; Mario Schölzel; Jaan Raik; Raimund Ubar (EWME, 2014)

Timing for virtual TMR in logic circuits. - Sebastian Müller 005; Tobias Koal; Mario Schölzel; Heinrich Theodor Vierhaus (IOLTS, 2014)

Vergleich der Beschreibung und Simulation einer Befehlssatzarchitektur in LISA und CoMet. - Roberto Urban; Kai Lehniger; Maximilian Heyne; Mario Schölzel; Heinrich Theodor Vierhaus (MBMV, 2014)

Redundancy evaluation process of processor components for permanent fault compensation. - Tobias Koal; Heinrich Theodor Vierhaus (AHS, 2015)

Combining Correction of Delay Faults and Transient Faults. - Tobias Koal; Stefan Scharoba; Heinrich Theodor Vierhaus (DDECS, 2015)

Compiler-Centred Microprocessor Design (CoMet) - From C-Code to a VHDL Model of an ASIP. - Roberto Urban; Mario Schölzel; Heinrich Theodor Vierhaus; Enrico Altmann; Horst Seelig (DDECS, 2015)

Detection and Correction of Logic Errors Using Extra Time Slots. - Davide Dicorato; Heinrich Theodor Vierhaus (GI-Jahrestagung, 2015)

Test eingebetteter Prozessoren im Zielsystem mit hoher diagnostischer Auflösung. - Christian Gleichner; Heinrich Theodor Vierhaus (GI-Jahrestagung, 2015)

Doktorandenprogramm der INFORMATIK 2015. - Ansgar Scherp; Steffen Becker 001; Heinrich Theodor Vierhaus (GI-Jahrestagung, 2015)

Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen. - Mario Schölzel; Heinrich Theodor Vierhaus (GI-Jahrestagung, 2015)

Multiple fault testing in systems-on-chip with high-level decision diagrams. - Raimund Ubar; Stephen Adeboye Oyeniran; Mario Schölzel; Heinrich Theodor Vierhaus (IDT, 2015)

A multi-layer software-based fault-tolerance approach for heterogenous multi-core systems. - Sebastian Müller 005; Tobias Koal; Stefan Scharoba; Heinrich Theodor Vierhaus; Mario Schölzel (LATS, 2015)

Error resilience in nano-electronic digital circuits and systems. - Heinrich Theodor Vierhaus (SPA, 2015)

Test of automotive embedded processors with high diagnostic resolution. - Christian Gleichner; Heinrich Theodor Vierhaus (DDECS, 2016)

An Interactive Design Space Exploration Tool for Dependable Integrated Circuits. - Stefan Scharoba; Heinrich Theodor Vierhaus (DSD, 2016)

A comprehensive software-based self-test and self-repair method for statically scheduled superscalar processors. - Mario Schölzel; Tobias Koal; Sebastian Müller 005; Stefan Scharoba; Stephanie Roder; Heinrich Theodor Vierhaus (LATS, 2016)

Iterative error correction with double/triple error detection. - Petr Pfeifer; Heinrich Theodor Vierhaus (SPA, 2016)

Non-Cyclic Design Space Exploration for ASIPs - Compiler-Centered Microprocessor Design (CoMet). - Roberto Urban; Heinrich Theodor Vierhaus; Mario Schölzel; Enrico Altmann; Horst Seelig (J. Circuits Syst. Comput., 2016)

Fault detection and self repair in Hsiao-code FEC circuits. - Davide Dicorato; Petr Pfeifer; Heinrich Theodor Vierhaus (DDECS, 2017)

On comparison of robust configurable FPGA encoders for dependable industrial communication systems. - Petr Pfeifer; Farnoosh Hosseinzadeh; Heinrich Theodor Vierhaus (IOLTS, 2017)

Fast power overhead prediction for hardware redundancy-based fault tolerance. - Stefan Scharoba; Heinrich Theodor Vierhaus (IOLTS, 2017)

The coarse and fine granular fault tolerance techniques in FPGA-based processors. - Farnoosh Hosseinzadeh; Petr Pfeifer; Heinrich Theodor Vierhaus (SPA, 2017)

Forward error correction in wireless communication systems for industrial applications. - Petr Pfeifer; Heinrich Theodor Vierhaus (SPA, 2017)

Test and Diagnosis of Automotive Embedded Processors via High-Speed Standard Interfaces. - Christian Gleichner; Heinrich Theodor Vierhaus (J. Circuits Syst. Comput., 2017)

Optimal Dependability and Fine Granular Error Resilience Methodology for Reconfigurable Systems. - Farnoosh Hosseinzadeh; Petr Pfeifer; Heinrich Theodor Vierhaus (DSD, 2018)

RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality. - Heinrich Theodor Vierhaus; Maksim Jenihhin; Matteo Sonza Reorda (EWME, 2018)

Migrating Electronic Systems from Fault Tolerant Computing to Error Resilience. - Heinrich Theodor Vierhaus (SPA, 2018)

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. - Maksim Jenihhin; Said Hamdioui; Matteo Sonza Reorda; Milos Krstic; Peter Langendörfer; Christian Sauer 001; Anton Klotz; Michael Hübner 001; Jörg Nolte; Heinrich Theodor Vierhaus; Georgios N. Selimis; Dan Alexandrescu; et al. (DATE, 2020)