Transient latch-up: experimental analysis and device simulation. - S. Bargstädt-Franke; Wolfgang Stadler; Kai Esmark; Martin Streibl; Krzysztof Domanski; Horst A. Gieser; Heinrich Wolf; Waclaw Bala (Microelectron. Reliab., 2005)

A Dedicated TLP Set-Up to Investigate the ESD Robustness of RF Elements and Circuits. - Heinrich Wolf; Horst A. Gieser; Wolfgang Soldner; Harald Gossner (Microelectron. Reliab., 2005)

Capacitively coupled transmission line pulsing cc-TLP–a traceable and reproducible stress method in the CDM-domain. - Heinrich Wolf; Horst A. Gieser; Wolfgang Stadler; Wolfgang Wilkening (Microelectron. Reliab., 2005)

Transient-induced latch-up test setup for wafer-level and package-level. - Detlef Bonfert; Horst A. Gieser; Heinrich Wolf; M. Frank; A. Konrad; J. Schulz (Microelectron. Reliab., 2006)

ESD Susceptibility of Submicron Air Gaps. - Heinrich Wolf; Horst A. Gieser; Detlef Bonfert; Markus Hauser (Microelectron. Reliab., 2006)

Investigating the CDM susceptibility of IC's at package and wafer level by capacitive coupled TLP. - Heinrich Wolf; Horst A. Gieser; Dirk Walter (Microelectron. Reliab., 2009)