Optimization of advanced MOS technologies for narrow distribution of circuit performance. - Heinz Hoenigschmid; Mitiko Miura-Manausch; Odin Prigge; Alexander Rahm; Dominique Savignac (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. - Toshiaki Kirihata; Gerhard Mueller; Brian Ji; Gerd Frankowsky; Joseph M. Ross; Hartmud Terletzki; Dmitry G. Netis; Oliver Weinfurtner; David R. Hanson; Gabriel Daniel; Louis Lu-Chen Hsu; Daniel W. Storaska; et al. (IEEE J. Solid State Circuits, 1999)

A robust 8F2 ferroelectric RAM cell with depletion device (DeFeRAM). - Georg Braun; Heinz Hoenigschmid; Tobias Schlager; Werner Weber (IEEE J. Solid State Circuits, 2000)

A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. - Heinz Hoenigschmid; Alexander Frey; John K. DeBrosse; Toshiaki Kirihata; Gerhard Mueller; Daniel W. Storaska; Gabriel Daniel; Gerd Frankowsky; Kevin P. Guay; David R. Hanson; Louis Lu-Chen Hsu; Brian Ji; et al. (IEEE J. Solid State Circuits, 2000)

A high-speed 128-kb MRAM core for future universal memory applications. - John K. DeBrosse; Dietmar Gogl; Alexander Bette; Heinz Hoenigschmid; Raphael Robertazzi; Christian Arndt; Daniel Braun 011; D. Casarotto; Robert Havreluk; Stefan Lammers; Werner Obermaier; William R. Reohr; et al. (IEEE J. Solid State Circuits, 2004)

A 16-Mb MRAM featuring bootstrapped write drivers. - Dietmar Gogl; Christian Arndt; John C. Barwin; Alexander Bette; John K. DeBrosse; Earl T. Gow; Heinz Hoenigschmid; Stefan Lammers; Mark C. Lamorey; Yu Lu; Tom Maffitt; Kim Maloney; et al. (IEEE J. Solid State Circuits, 2005)

Signal-Margin-Screening for Multi-Mb MRAM. - Heinz Hoenigschmid; P. Beer; Alexander Bette; R. Dittrich; R. Gardic; Dietmar Gogl; Stefan Lammers; J. Schmid; Laith Altimime; Serge Bournat; Gerhard Müller (ISSCC, 2006)

A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control. - Stefan Dietrich; Michael Angerbauer; Milena Ivanov; Dietmar Gogl; Heinz Hoenigschmid; Michael Kund; Corvin Liaw; Michael Markert; Ralf Symanczyk; Laith Altimime; Serge Bournat; Gerhard Müller (IEEE J. Solid State Circuits, 2007)

75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques. - Rex Kho; David Boursin; Martin Brox; Peter Gregorius; Heinz Hoenigschmid; Bianka Kho; Sabine Kieser; Daniel Kehrer; Maksim Kuzmenka; Udo Moeller; Pavel Veselinov Petkov; Manfred Plan; et al. (ISSCC, 2009)

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques. - Rex Kho; David Boursin; Martin Brox; Peter Gregorius; Heinz Hoenigschmid; Bianka Kho; Sabine Kieser; Daniel Kehrer; Maksim Kuzmenka; Udo Moeller; Pavel Veselinov Petkov; Manfred Plan; et al. (IEEE J. Solid State Circuits, 2010)