Test Case Generation from Mutants Using Model Checking Techniques. - Heinz Riener; Roderick Bloem; Görschwin Fey (ICST Workshops, 2011)

Model-based diagnosis versus error explanation. - Heinz Riener; Görschwin Fey (MEMOCODE, 2012)

FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation. - Heinz Riener; Görschwin Fey (SPIN, 2012)

Improving fault tolerance utilizing hardware-software-co-synthesis. - Heinz Riener; Stefan Frehse; Görschwin Fey (DATE, 2013)

Yet a Better Error Explanation Algorithm (Extended Abstract). - Heinz Riener; Görschwin Fey (MBMV, 2013)

MetaSMT: a unified interface to SMT-LIB2. - Heinz Riener; Mathias Soeken; Clemens Werther; Görschwin Fey; Rolf Drechsler (FDL, 2014)

A Logic for Cardinality Constraints (Extended Abstract). - Heinz Riener; Oliver Keszöcze; Rolf Drechsler; Görschwin Fey (MBMV, 2014)

Equivalence Checking on System Level Using a Priori Knowledge. - Niels Thole; Heinz Riener; Görschwin Fey (DDECS, 2015)

Execution Tracing of C Code for Formal Analysis (Extended Abstract). - Heinz Riener; Michael Kirkedal Thomsen; Görschwin Fey (MBMV, 2015)

Path-Based Program Repair. - Heinz Riener; Rüdiger Ehlers; Görschwin Fey (FESCA, 2015)

SMT-Based CPS Parameter Synthesis. - Heinz Riener; Robert Könighofer; Görschwin Fey; Roderick Bloem (ARCH@CPSWeek, 2016)

Designing reliable cyber-physical systems overview associated to the special session at FDL'16. - Gadi Aleksandrowicz; Eli Arbel; Roderick Bloem; Timon D. ter Braak; Sergei Devadze; Görschwin Fey; Maksim Jenihhin; Artur Jutman; Hans G. Kerkhoff; Robert Könighofer; Jan Malburg; Shiri Moran; et al. (FDL, 2016)

Equivalence checking on ESL utilizing a priori knowledge. - Niels Thole; Heinz Riener; Görschwin Fey (FDL, 2016)

Exact diagnosis using boolean satisfiability. - Heinz Riener; Görschwin Fey (ICCAD, 2016)

Counterexample-guided diagnosis. - Heinz Riener; Görschwin Fey (IVSW, 2016)

WCET overapproximation for software in the context of a Cyber-Physical System. - Niklas Krafczyk; Heinz Riener; Görschwin Fey (VLSI-SoC, 2016)

CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification. - Heinz Riener; Rüdiger Ehlers; Görschwin Fey (ASP-DAC, 2017)

Counterexample-Guided EF Synthesis of Boolean Functions. - Heinz Riener; Rüdiger Ehlers; Görschwin Fey (MBMV, 2017)

metaSMT: focus on your application and not on solver integration. - Heinz Riener; Finn Haedicke; Stefan Frehse; Mathias Soeken; Daniel Große; Rolf Drechsler; Görschwin Fey (Int. J. Softw. Tools Technol. Transf., 2017)

Formal methods for automated debugging. - Heinz Riener (2017)

Mining Latency Guarantees for RTL Designs. - Jan Malburg; Heinz Riener; Görschwin Fey (ISMVL, 2018)

Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model. - Cunxi Yu; Heinz Riener; Francesca Stradolini; Giovanni De Micheli (ISVLSI, 2018)

Size Optimization of MIGs with an Application to QCA and STMG Technologies. - Heinz Riener; Eleonora Testa; Luca G. Amarù; Mathias Soeken; Giovanni De Micheli (NANOARCH, 2018)

Design Understanding: From Logic to Specification*. - Görschwin Fey; Tara Ghasempouri; Swen Jacobs; Gianluca Martino; Jaan Raik; Heinz Riener (VLSI-SoC, 2018)

The EPFL Logic Synthesis Libraries. - Mathias Soeken; Heinz Riener; Winston Haaswijk; Giovanni De Micheli (CoRR, 2018)

Exact Synthesis of ESOP Forms. - Heinz Riener; Rüdiger Ehlers; Bruno Schmitt; Giovanni De Micheli (CoRR, 2018)

Scalable Generic Logic Synthesis: One Approach to Rule Them All. - Heinz Riener; Eleonora Testa; Winston Haaswijk; Alan Mishchenko; Luca G. Amarù; Giovanni De Micheli; Mathias Soeken (DAC, 2019)

On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis. - Heinz Riener; Winston Haaswijk; Alan Mishchenko; Giovanni De Micheli; Mathias Soeken (DATE, 2019)

Exact Synthesis of LTL Properties from Traces. - Heinz Riener (FDL, 2019)

Logic Optimization of Majority-Inverter Graphs. - Heinz Riener; Eleonora Testa; Winston Haaswijk; Alan Mishchenko; Luca G. Amarù; Giovanni De Micheli; Mathias Soeken (MBMV, 2019)

Evaluating ESOP Optimization Methods in Quantum Compilation Flows. - Giulia Meuli; Bruno Schmitt; Rüdiger Ehlers; Heinz Riener; Giovanni De Micheli (RC, 2019)

Synthesizing adaptive test strategies from temporal logic specifications. - Roderick Bloem; Görschwin Fey; Fabian Greif; Robert Könighofer; Ingo Pill; Heinz Riener; Franz Röck (Formal Methods Syst. Des., 2019)

Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle. - Victor N. Kravets; Jie-Hong R. Jiang; Heinz Riener (DATE, 2020)

Exact DAG-Aware Rewriting. - Heinz Riener; Alan Mishchenko; Mathias Soeken (DATE, 2020)

Revisiting Explicit Enumeration for Exact Synthesis. - Gianluca Martino; Heinz Riener; Görschwin Fey (DSD, 2020)

Automatic Uniform Quantum State Preparation Using Decision Diagrams. - Fereshte Mozafari; Mathias Soeken; Heinz Riener; Giovanni De Micheli (ISMVL, 2020)

Simulation-Guided Boolean Resubstitution. - Siang-Yun Lee; Heinz Riener; Alan Mishchenko; Robert K. Brayton; Giovanni De Micheli (CoRR, 2020)

Safety Synthesis Sans Specification. - Roderick Bloem; Hana Chockler; Masoud Ebrahimi 002; Dana Fisman; Heinz Riener (CoRR, 2020)

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. - Eleonora Testa; Mathias Soeken; Heinz Riener; Luca G. Amarù; Giovanni De Micheli (IACR Cryptol. ePrint Arch., 2020)

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits. - Eleonora Testa; Siang-Yun Lee; Heinz Riener; Giovanni De Micheli (ASP-DAC, 2021)

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies. - Shubham Rai; Heinz Riener; Giovanni De Micheli; Akash Kumar 001 (DATE, 2021)

From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++. - Bruno Schmitt; Fereshte Mozafari; Giulia Meuli; Heinz Riener; Giovanni De Micheli (DATE, 2021)

Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition. - Siang-Yun Lee; Heinz Riener; Giovanni De Micheli (DDECS, 2021)

Optimizing Adiabatic Quantum-Flux-Parametron (AQFP) Circuits using an Exact Database. - Dewmini Sudara Marakkalage; Heinz Riener; Giovanni De Micheli (NANOARCH, 2021)

Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits. - Siang-Yun Lee; Heinz Riener; Giovanni De Micheli (CoRR, 2021)

Three-Input Gates for Logic Synthesis. - Dewmini Sudara Marakkalage; Eleonora Testa; Heinz Riener; Alan Mishchenko; Mathias Soeken; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Versatile Mapping Approach for Technology Mapping and Graph Optimization. - Alessandro Tempia Calvino; Heinz Riener; Shubham Rai; Akash Kumar 001; Giovanni De Micheli (ASP-DAC, 2022)

Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. - Heinz Riener; Siang-Yun Lee; Alan Mishchenko; Giovanni De Micheli (ASP-DAC, 2022)

Beyond local optimality of buffer and splitter insertion for AQFP circuits. - Siang-Yun Lee; Heinz Riener; Giovanni De Micheli (DAC, 2022)

An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications. - Siang-Yun Lee; Heinz Riener; Giovanni De Micheli (CoRR, 2022)

A Simulation-Guided Paradigm for Logic Synthesis and Verification. - Siang-Yun Lee; Heinz Riener; Alan Mishchenko; Robert K. Brayton; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits. - Shubham Rai; Alessandro Tempia Calvino; Heinz Riener; Giovanni De Micheli; Akash Kumar 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration. - Siang-Yun Lee; Alessandro Tempia Calvino; Heinz Riener; Giovanni De Micheli (DAC, 2024)

Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron. - Siang-Yun Lee; Alessandro Tempia Calvino; Heinz Riener; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)