Circuit Optimization Driven by Worst-Case Distances. - Kurt Antreich; Helmut E. Graeb (ICCAD, 1991)

Design verification considering manufacturing tolerances by using worst-caste distances. - Helmut E. Graeb; Claudia U. Wieser; Kurt Antreich (EURO-DAC, 1992)

Circuit yield optimization by analyzing performance statistics. - Helmut E. Graeb; Reiner E. Lederle (Microprocess. Microprogramming, 1992)

Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances. - Helmut E. Graeb; Claudia U. Wieser; Kurt Antreich (DAC, 1993)

Schaltkreisoptimierung mit Worst-Case-Abständen als Zielgrössen. - Helmut Gräb (Shaker, 1993)

Fast transient power and noise estimation for VLSI circuits. - Wolfgang T. Eisenmann; Helmut E. Graeb (ICCAD, 1994)

Circuit analysis and optimization driven by worst-case distances. - Kurt Antreich; Helmut E. Graeb; Claudia U. Wieser (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Design based analog testing by Characteristic Observation Inference. - Walter M. Lindermeir; Helmut E. Graeb; Kurt Antreich (ICCAD, 1995)

Hierarchical Characterization of Analog Integrated CMOS Circuits. - Josef Eckmüller; Martin Groepl; Helmut E. Graeb (DATE, 1998)

Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults. - Walter M. Lindermeir; Thomas J. Vogels; Helmut E. Graeb (DATE, 1998)

Fast calculation of analog circuits' feasibility regions by low level functional measures. - Stephan Zizala; Josef Eckmüller; Helmut Gräb (ICECS, 1998)

Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints. - Robert Schwencker; Josef Eckmüller; Helmut E. Graeb; Kurt Antreich (DATE, 1999)

Simulationsbasierter Testentwurf für gemischt analog-digitale Systeme. - Michael Pronath; Volker Glöckel; Helmut Gräb; Kurt Antreich (Informationstechnik Tech. Inform., 1999)

Analog testing by characteristic observation inference. - Walter M. Lindermeir; Helmut E. Graeb; Kurt Antreich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

WiCkeD: analog circuit synthesis incorporating mismatch. - Kurt Antreich; Josef Eckmüller; Helmut Graeb; Michael Pronath; Frank Schenkel; Robert Schwencker; Stephan Zizala (CICC, 2000)

The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits. - Robert Schwencker; Frank Schenkel; Helmut E. Graeb; Kurt Antreich (DATE, 2000)

A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits. - Michael Pronath; Volker Gloeckel; Helmut E. Graeb (ICCAD, 2000)

A fast method for identifying matching-relevant transistor pairs. - Frank Schenkel; Michael Pronath; Helmut Graeb; Kurt Antreich (CICC, 2001)

Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search. - Frank Schenkel; Michael Pronath; Stephan Zizala; Robert Schwencker; Helmut E. Graeb; Kurt Antreich (DAC, 2001)

The Sizing Rules Method for Analog Integrated Circuit Design. - Helmut E. Graeb; Stephan Zizala; Josef Eckmüller; Kurt Antreich (ICCAD, 2001)

A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits. - Michael Pronath; Helmut E. Graeb; Kurt Antreich (DATE, 2002)

Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets. - Robert Schwencker; Frank Schenkel; Michael Pronath; Helmut E. Graeb (DATE, 2002)

Performance trade-off analysis of analog circuits by normal-boundary intersection. - Guido Stehr; Helmut E. Graeb; Kurt Antreich (DAC, 2003)

Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification. - Guido Stehr; Michael Pronath; Frank Schenkel; Helmut E. Graeb; Kurt Antreich (ICCAD, 2003)

Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing. - Guido Stehr; Helmut E. Graeb; Kurt Antreich (ICCAD, 2004)

Deterministic approaches to analog performance space exploration (PSE). - Daniel Mueller 001; Guido Stehr; Helmut E. Graeb; Ulf Schlichtmann (DAC, 2005)

Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen. - Daniel Mueller 001; Guido Stehr; Helmut E. Graeb; Ulf Schlichtmann (GI Jahrestagung (1), 2005)

A CPPLL hierarchical optimization methodology considering jitter, power and locking time. - Jun Zou; Daniel Mueller 001; Helmut E. Graeb; Ulf Schlichtmann (DAC, 2006)

Fast evaluation of analog circuit structures by polytopal approximations. - Daniel Mueller 001; Guido Stehr; Helmut E. Graeb; Ulf Schlichtmann (ISCAS, 2006)

Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts. - Jun Zou; Helmut Graeb; Daniel Mueller 001; Ulf Schlichtmann (CICC, 2007)

Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. - Daniel Mueller 001; Helmut E. Graeb; Ulf Schlichtmann (DATE, 2007)

Pareto-Front Computation and Automatic Sizing of CPPLLs. - Jun Zou; Daniel Mueller 001; Helmut E. Graeb; Ulf Schlichtmann (ISQED, 2007)

Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination. - Guido Stehr; Helmut E. Graeb; Kurt Antreich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

From Transistor to PLL - Analogue Design and EDA Methods. - David M. Binkley; Helmut E. Graeb; Georges G. E. Gielen; Jaijeet S. Roychowdhury (DATE, 2008)

Sizing Rules for Bipolar Analog Circuit Design. - Tobias Massier; Helmut E. Graeb; Ulf Schlichtmann (DATE, 2008)

Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions. - Martin Strasser; Michael Eick; Helmut Gräb; Ulf Schlichtmann; Frank M. Johannes (ICCAD, 2008)

A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters. - Michael Pehl; Tobias Massier; Helmut E. Graeb; Ulf Schlichtmann (ICCD, 2008)

The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. - Tobias Massier; Helmut E. Graeb; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Formal approaches to analog circuit verification. - Erich Barke; Darius Grabowski; Helmut Graeb; Lars Hedrich; Stefan Heinen; Ralf Popp; Sebastian Steinhorst; Yifan Wang 001 (DATE, 2009)

Analog layout synthesis - Recent advances in topological approaches. - Helmut Gräb; Florin Balasa; Rafael Castro-López; Yu-Wei Chang 002; Francisco V. Fernández 001; Mark Po-Hung Lin; Martin Strasser (DATE, 2009)

A free-shape router for analog and RF applications. - Engin Avci; Martin Strasser; Helmut Graeb; Ulf Schlichtmann (ECCTD, 2009)

Degradation-aware analog design flow for lifetime yield analysis and optimization. - Xin Pan; Helmut Graeb (ICECS, 2009)

Pareto optimization of analog circuits considering variability. - Helmut Graeb; Daniel Mueller-Gritschneder; Ulf Schlichtmann (Int. J. Circuit Theory Appl., 2009)

A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems. - Daniel Mueller-Gritschneder; Helmut E. Graeb; Ulf Schlichtmann (SIAM J. Optim., 2009)

Reliability analysis of analog circuits using quadratic lifetime worst-case distance prediction. - Xin Pan; Helmut Graeb (CICC, 2010)

Computation of yield-optimized Pareto fronts for analog integrated circuit specifications. - Daniel Mueller-Gritschneder; Helmut Graeb (DATE, 2010)

Sizing analog circuits using an SQP and Branch and Bound based approach. - Michael Pehl; Michael Zwerger; Helmut E. Graeb (ICECS, 2010)

Automatic generation of hierarchical placement rules for analog integrated circuits. - Michael Eick; Martin Strasser; Helmut E. Graeb; Ulf Schlichtmann (ISPD, 2010)

Reliability analysis of analog circuits by lifetime yield prediction using worst-case distance degradation rate. - Xin Pan; Helmut Graeb (ISQED, 2010)

Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits. - Michael Eick; Martin Strasser; Kun Lu 005; Ulf Schlichtmann; Helmut E. Graeb (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Constraint-Based Layout-Driven Sizing of Analog Circuits. - Husni M. Habal; Helmut Graeb (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

ITRS 2011 Analog EDA Challenges and Approaches. - Helmut Graeb (DATE, 2012)

Tolerance Design of Analog Circuits using a Branch-and-Bound Based Approach. - Michael Pehl; Helmut E. Graeb (J. Circuits Syst. Comput., 2012)

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area. - Xin Pan; Helmut Graeb (Microelectron. Reliab., 2012)

MARS: Matching-Driven Analog Sizing. - Michael Eick; Helmut E. Graeb (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies. - Veit Kleeberger; Helmut E. Graeb; Ulf Schlichtmann (DAC, 2013)

Evaluating analog circuit performance in light of MOSFET aging at different time scales. - Husni M. Habal; Helmut E. Graeb (ICICDT, 2013)

Advanced performance metrics for Physical Unclonable Functions. - Michael Pehl; Akshara Ranjit Punnakkal; Matthias Hiller; Helmut Graeb (ISIC, 2014)

Detection of asymmetric aging-critical voltage conditions in analog power-down mode. - Michael Zwerger; Helmut E. Graeb (DATE, 2015)

Power-Down Circuit Synthesis for Analog/Mixed-Signal. - Michael Zwerger; Maximilian Neuner; Helmut E. Graeb (ICCAD, 2015)

A pre-search assisted ILP approach to analog integrated circuit routing. - Chia-Yu Wu; Helmut Graeb; Jiang Hu (ICCD, 2015)

A fast analytical approach for static power-down mode analysis. - Michael Zwerger; Pantelis-Rafail Vlachas; Helmut Graeb (ICECS, 2015)

Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis. - Florin Burcea; Husni M. Habal; Helmut E. Graeb (DAC, 2016)

Power-down synthesis for analog circuits including switch sizing. - Michael Zwerger; Gaurav Shrivastava; Helmut Graeb (SMACD, 2016)

Efficient Evaluation of Physical Unclonable Functions Using Entropy Measures. - Michael Pehl; Matthias Hiller; Helmut Graeb (J. Circuits Syst. Comput., 2016)

A step-accurate model for the trapping and release of charge carriers suitable for the transient simulation of analog circuits. - Husni M. Habal; Helmut Graeb (Microelectron. Reliab., 2016)

A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity. - Florin Burcea; Husni M. Habal; Helmut E. Graeb (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths. - Mark Po-Hung Lin; Po-Hsun Chang; Shuenn-Yuh Lee; Helmut E. Graeb (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC. - Nai-Chen Chen; Pang-Yen Chou; Helmut E. Graeb; Mark Po-Hung Lin (DATE, 2017)

A new robustness optimization methodology for MEMS-IC systems. - Florin Burcea; Andreas Herrmann; Aditya Gupta; Helmut Graeb (SMACD, 2017)

Realistic worst-case parameter sets for MEMS technologies. - Andreas Herrmann; Christof Hielscher; Alexander Mueller; Gisbert Hoelzer; Helmut Graeb (SMACD, 2017)

Analog Power-Down Synthesis. - Michael Zwerger; Maximilian Neuner; Helmut Graeb (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters. - Pang-Yen Chou; Nai-Chen Chen; Mark Po-Hung Lin; Helmut Graeb (IEEE Trans. Very Large Scale Integr. Syst., 2017)

On enabling diagnosis for 1-Pin Test fails in an industrial flow. - Daniel Tille; Benedikt Gottinger; Ulrike Pfannkuchen; Helmut Graeb; Ulf Schlichtmann (ASP-DAC, 2018)

MEMS-IC Optimization Considering Design Parameters and Manufacturing Variation from both Mechanical and Electrical Side. - Florin Burcea; Andreas Herrmann; Bing Li 005; Helmut Graeb (ICECS, 2018)

Design-dependent Monitors Based on Delay Sensitivity Tracking. - Jahnavi Kasturi Rangan; Nasim Pour Aryan; Lantao Wang; Jens Bargfrede; Christian Funke; Helmut Graeb (ICECS, 2018)

Reverse Engineering of Cryptographic Cores by Structural Interpretation Through Graph Analysis. - Michael Werner; Bernhard Lippmann; Johanna Baehr 001; Helmut Gräb (IVSW, 2018)

Bringing Analog Design Tools to Security: Modeling and Optimization of a Low Area Probing Detector. - Andreas Herrmann; Michael Weiner 004; Michael Pehl; Helmut Graeb (SMACD, 2018)

A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications. - Francesco Santoro; Rüdiger Kuhn; Neil Gibson; Nicola Rasera; Thomas Tost; Helmut Graeb; Bernhard Wicht; Ralf Brederlow (IEEE J. Solid State Circuits, 2018)

Integrated flow for reverse engineering of nanoscale technologies. - Bernhard Lippmann; Michael Werner; Niklas Unverricht; Aayush Singla; Peter Egger; Anja Dübotzky; Horst A. Gieser; Martin Rasche; Oliver Kellermann; Helmut Graeb (ASP-DAC, 2019)

Cross-Layer Interactions in CPS for Performance and Certification. - Samarjit Chakraborty; James H. Anderson; Martin Becker 001; Helmut Graeb; Samiran Halder; Ravindra Metta; Lothar Thiele; Stavros Tripakis; Anand Yeolekar (DATE, 2019)

Constraint-Programmed Initial Sizing of Analog Operational Amplifiers. - Inga Abel; Maximilian Neuner; Helmut Graeb (ICCD, 2019)

Inversion-Coefficient-Aware Yield Optimization of Analog Circuits. - Florin Burcea; Helmut Graeb (ICECS, 2019)

Verification of Physical Chip Layouts Using GDSII Design Data. - Aayush Singla; Bernhard Lippmann; Helmut Graeb (IVSW, 2019)

Power-Down Mode Verification for Hierarchical Analog Circuits. - Maximilian Neuner; Helmut Graeb (SMACD, 2019)

A 30 ns 16 Mb 2 b/cell Embedded Flash with Ramped Gate Time-Domain Sensing Scheme for Automotive Application. - Sebastian Kiesel; Thomas Kern; Bernhard Wicht; Helmut Graeb (VLSI-DAT, 2019)

Derivative free methodologies for circuit worst case analysis. - Vittorio Latorre; Husni M. Habal; Helmut Graeb; Stefano Lucidi (Optim. Lett., 2019)

MEMS-IC Robustness Optimization Considering Electrical and Mechanical Design and Process Parameters. - Florin Burcea; Andreas Herrmann; Bing Li 005; Helmut Graeb (ACM Trans. Design Autom. Electr. Syst., 2019)

Synergetic Algorithm for Power-Down Synthesis. - Maximilian Neuner; Helmut Graeb (ECCTD, 2020)

Structural Synthesis of Operational Amplifiers Based on Functional Block Modeling. - Inga Abel; Helmut Graeb (ICCAD, 2020)

Hierarchical Analog Power-Down Synthesis. - Maximilian Neuner; Helmut Graeb (ICECS, 2020)

Recovery of 2D and 3D Layout Information through an Advanced Image Stitching Algorithm using Scanning Electron Microscope Images. - Aayush Singla; Bernhard Lippmann; Helmut Graeb (ICPR, 2020)

Modeling and Optimization of a Microprobe Detector for Area and Yield Improvement. - Alessandro Girardi; Helmut Graeb (SBCCI, 2020)

A Hierarchical Performance Equation Library for Op-Amp Design. - Inga Abel; Maximilian Neuner; Helmut Graeb (CoRR, 2020)

Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies. - Bernhard Lippmann; Niklas Unverricht; Aayush Singla; Matthias Ludwig 005; Michael Werner; Peter Egger; Anja Dübotzky; Helmut Gräb; Horst A. Gieser; Martin Rasche; Oliver Kellermann (Integr., 2020)

Verification and revision of the power-down mode for hierarchical analog circuits. - Maximilian Neuner; Helmut Graeb (Integr., 2020)

PASTEL: Parasitic Matching-Driven Placement and Routing of Capacitor Arrays With Generalized Ratios in Charge-Redistribution SAR-ADCs. - Ye X. Ding; Florin Burcea; Husni M. Habal; Helmut E. Graeb (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Synthesis of DDRO Timing Monitors by Delay-Tracking and Static Timing Analysis. - Jahnavi Kasturi Rangan; Nasim Pour Aryan; Jens Bargfrede; Lantao Wang; Christian Funke; Helmut Graeb (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Library-free Structure Recognition for Analog Circuits. - Maximilian Neuner; Inga Abel; Helmut Graeb (DATE, 2021)

An Efficient Programming Framework for Memristor-based Neuromorphic Computing. - Grace Li Zhang; Bing Li 005; Xing Huang 001; Chen Shen; Shuhang Zhang; Florin Burcea; Helmut Graeb; Tsung-Yi Ho; Hai Li 001; Ulf Schlichtmann (DATE, 2021)

Structure Synthesis of Op-Amps by Functional Block Composition. - Inga Abel; Helmut Graeb (CoRR, 2021)

COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing. - Inga Abel; Maximilian Neuner; Helmut Graeb (Integr., 2021)

Analog Synthesis - The Deterministic Way. - Helmut Graeb (ISPD, 2022)

A functional block decomposition method for automatic op-amp design. - Inga Abel; Maximilian Neuner; Helmut Graeb (Integr., 2022)

A Hierarchical Performance Equation Library for Basic Op-Amp Design. - Inga Abel; Maximilian Neuner; Helmut E. Graeb (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition. - Inga Abel; Helmut Graeb (ACM Trans. Design Autom. Electr. Syst., 2022)

Learning from the Implicit Functional Hierarchy in an Analog Netlist. - Helmut Graeb; Markus Leibl (ISPD, 2023)

Optimizer-Free Sizing of OpAmps Leveraging Structural and Functional Properties. - Markus Leibl; Helmut Graeb (SMACD, 2024)

Inverse Analog IC Sizing and Exploration through Diffusion Models and Structural Knowledge. - Filipe Azevedo 001; Markus Leibl; Ricardo Martins 003; Helmut Graeb (SMACD, 2025)