Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. - Andreas Ast; Reiner W. Hartenstein; Rainer Kress 002; Helmut Reinig; Karin Schmidt (FPL, 1992)

A dynamically reconfigurable wavefront array architecture for evaluation of expressions. - Reiner W. Hartenstein; Rainer Kress 002; Helmut Reinig (ASAP, 1994)

Data-Procedural Languages for FPL-based Machines. - Andreas Ast; Jürgen Becker 001; Reiner W. Hartenstein; Rainer Kress 002; Helmut Reinig; Karin Schmidt (FPL, 1994)

A New FPGA Architecture for Word-Oriented Datapaths. - Reiner W. Hartenstein; Rainer Kress 002; Helmut Reinig (FPL, 1994)

A Parallelizing Compilation Method for the Map-oriented Machine. - Reiner W. Hartenstein; Jürgen Becker 001; Rainer Kress 002; Helmut Reinig; Karin Schmidt (ASAP, 1995)

CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. - Reiner W. Hartenstein; Jürgen Becker 001; Rainer Kress 002; Helmut Reinig (VLSI Design, 1996)

High-performance computing using a reconfigurable accelerator. - Reiner W. Hartenstein; Jürgen Becker 001; Rainer Kress 002; Helmut Reinig (Concurr. Pract. Exp., 1996)

Codevelopment of long haul ISDN transceiver and design methodology improves time to market. - Markus Brandstetter; Torsten Harms; Helmut Reinig; Michael Vanrompay (ICECS, 1998)

A scalable architecture for custom computing. - Helmut Reinig (1999)

An Efficient Weighted-Round-Robin Algorithm for Multiprocessor Architectures. - Sören Sonntag; Helmut Reinig (Annual Simulation Symposium, 2008)

NoC topology exploration for mobile multimedia applications. - Andreas Lankes; Andreas Herkersdorf; Sören Sonntag; Helmut Reinig (ICECS, 2009)

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks. - Andreas Lankes; Thomas Wild; Andreas Herkersdorf; Sören Sonntag; Helmut Reinig (NOCS, 2010)

Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study. - Hervé Tatenguem; Daniele Ludovici; Alessandro Strano; Davide Bertozzi; Helmut Reinig (NoCArc@MICRO, 2011)

Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs. - Vladimir Todorov; Alberto Ghiribaldi; Helmut Reinig; Davide Bertozzi; Ulf Schlichtmann (CODES+ISSS, 2012)

Automated construction of a cycle-approximate transaction level model of a memory controller. - Vladimir Todorov; Daniel Mueller-Gritschneder; Helmut Reinig; Ulf Schlichtmann (DATE, 2012)

A spectral clustering approach to application-specific network-on-chip synthesis. - Vladimir Todorov; Daniel Mueller-Gritschneder; Helmut Reinig; Ulf Schlichtmann (DATE, 2013)

Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies. - Vladimir Todorov; Daniel Mueller-Gritschneder; Helmut Reinig; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)