Algorithm Driven Power-Timing Optimization Methodology for CMOS Digital Circuits Considering PVTA Variations. - Hema Sai Kalluru; Prasenjit Saha; Andleeb Zahra; Zia Abbas (ISCAS, 2021)

Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence. - Prasenjit Saha; Salman Ahmed; Hema Sai Kalluru; Zia Abbas (ISCAS, 2021)

PVT and Aging Degradation Invariant Automated Optimization Approach for CMOS Low-Power High-Performance VLSI Circuits. - Hema Sai Kalluru; Prasenjit Saha; Andleeb Zahra; Zia Abbas (ISQED, 2021)

Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence. - Prasenjit Saha; Hema Sai Kalluru; Zia Abbas (VLSID, 2021)