Driver waveform computation for timing analysis with multiple voltage threshold driver models. - Peter Feldmann; Soroush Abbaspour; Debjit Sinha; Gregory Schaeffer; Revanta Banerji; Hemlata Gupta (DAC, 2008)

Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure. - Ravi Ledalla; Debjit Sinha; Adil Bhanji; Chaobo Li; Gregory Schaeffer; Hemlata Gupta; Jennifer Basile (DATE, 2021)

Improving LLM-Powered EDA Assistants with RAFT. - Luyao Shi; Michael Kazda; Charles Schmitter; Hemlata Gupta (CoRR, 2025)