Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs. - Yueming Yang; Heng Quan; Zewen Shi; Xiaoyang Zeng; Zhiyi Yu (ASICON, 2011)

A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost. - Yan Ying; Kaidi You; Liyang Zhou; Heng Quan; Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng (ISCAS, 2012)

An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. - Zhiyi Yu; Kaidi You; Ruijin Xiao; Heng Quan; Peng Ou; Yan Ying; Haofan Yang 001; Ming-e Jing; Xiaoyang Zeng (ISSCC, 2012)

A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array. - Peng Ou; Jiajie Zhang; Heng Quan; Yi Li; Maofei He; Zheng Yu 001; Xueqiu Yu; Shile Cui; Jie Feng; Shikai Zhu; Jie Lin; Ming-e Jing; et al. (ISSCC, 2013)

A 16-Core Processor With Shared-Memory and Message-Passing Communications. - Zhiyi Yu; Ruijin Xiao; Kaidi You; Heng Quan; Peng Ou; Zheng Yu 001; Maofei He; Jiajie Zhang; Yan Ying; Haofan Yang 001; Jun Han 003; Xu Cheng 002; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Routing Protocol for Heterogeneous Wireless Sensor Networks Based on a Modified Grey Wolf Optimizer. - Xiaoqiang Zhao; Shaoya Ren; Heng Quan; Qiang Gao 015 (Sensors, 2020)

Multi-Level Spatiotemporal Network for Video Summarization. - Ming Yao; Yu Bai 021; Wei Du; Xuejun Zhang; Heng Quan; Fuli Cai; Hongwei Kang (ACM Multimedia, 2022)